


default search action
"High throughput 32-bit AES implementation in FPGA."
Chi-Jeng Chang et al. (2008)
- Chi-Jeng Chang, Chi-Wu Huang, Kuo-Huang Chang, Yi-Cheng Chen, Chung-Cheng Hsieh:

High throughput 32-bit AES implementation in FPGA. APCCAS 2008: 1806-1809

manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.


Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID












