Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques.

Chun-Kai Hsu Li-Ming Denq Mao-Yin Wang Jing-Jia Liou Chih-Tsun Huang Cheng-Wen Wu Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. 245-250 2008 ATS https://doi.org/10.1109/ATS.2008.19 https://doi.ieeecomputersociety.org/10.1109/ATS.2008.19 conf/ats/2008 db/conf/ats/ats2008.html#HsuDWLHW08