<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<inproceedings key="conf/irps/PanarellaKSVSCLTARKA23" mdate="2026-02-25">
<author>L. Panarella</author>
<author>Ben Kaczer</author>
<author>Quentin Smets</author>
<author>Devin Verreck</author>
<author orcid="0000-0003-1533-7055">Tom Schram</author>
<author>Daire Cott</author>
<author>Dennis Lin</author>
<author>Stanislav Tyaginov</author>
<author>Inge Asselberghs</author>
<author>Cesar J. Lockhart de la Rosa</author>
<author>Gouri Sankar Kar</author>
<author>Valeri Afanas'ev</author>
<title>Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs.</title>
<pages>1-6</pages>
<year>2023</year>
<booktitle>IRPS</booktitle>
<ee>https://doi.org/10.1109/IRPS48203.2023.10117803</ee>
<crossref>conf/irps/2023</crossref>
<url>db/conf/irps/irps2023.html#PanarellaKSVSCLTARKA23</url>
</inproceedings>
</dblp>
