<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<inproceedings key="conf/isscc/HusseinVSP17" mdate="2017-05-17">
<author>Ahmed I. Hussein</author>
<author>Sriharsha Vasadi</author>
<author>Mazen Soliman</author>
<author>Jeyanandh Paramesh</author>
<title>19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter.</title>
<pages>326-327</pages>
<year>2017</year>
<booktitle>ISSCC</booktitle>
<ee>https://doi.org/10.1109/ISSCC.2017.7870393</ee>
<crossref>conf/isscc/2017</crossref>
<url>db/conf/isscc/isscc2017.html#HusseinVSP17</url>
</inproceedings></dblp>
