<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<article key="journals/tvlsi/LernerYT19" mdate="2020-03-11">
<author orcid="0000-0002-6292-7069">Scott Lerner</author>
<author>Isikcan Yilmaz</author>
<author orcid="0000-0002-7631-5696">Baris Taskin</author>
<title>Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors.</title>
<pages>700-710</pages>
<year>2019</year>
<volume>27</volume>
<journal>IEEE Trans. Very Large Scale Integr. Syst.</journal>
<number>3</number>
<ee>https://doi.org/10.1109/TVLSI.2018.2878664</ee>
<url>db/journals/tvlsi/tvlsi27.html#LernerYT19</url>
</article></dblp>
