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Cloud data warehouse to power your data-driven innovation
BigQuery is a serverless and cost-effective enterprise data warehouse that works across clouds and scales with your data.
BigQuery Studio provides a single, unified interface for all data practitioners of various coding skills to simplify analytics workflows from data ingestion and preparation to data exploration and visualization to ML model creation and use. It also allows you to use simple SQL to access Vertex AI foundational models directly inside BigQuery for text processing tasks, such as sentiment analysis, entity extraction, and many more without having to deal with specialized models.
OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver sourcecode.
CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C for
Win32, bus easily portable for other platforms
The Affordable BIOS Restoration Tool provides VHDL and C code to recover from failed BIOS upgrades using affordable CPLD's. EEPROM's and Flash chips can be restored with this flash programmer. Interfaces for DIP and tsop packages are being developed.
X-RT: A portable multiprocessor real-time scheduling framework
This project contains the material discussed in my PhD dissertation, entitled "Hardware/Software Design of Dynamic Real-Time Schedulers for Embedded Multiprocessor Systems."
The sourcecode is available in the SVN repository: https://sourceforge.net/p/xrt/code/6/tree/trunk/
and consists in two folders:
1) /X-RT : A portable multiprocessor scheduling framework supporting scheduling periodic real-time tasks according to the G-EDF (Global Earliest Deadline First) scheduling platform. Current version supports major POSIX systems (Linux, QNX).
2) Hardware_GEDF_Scheduler: is a hardware implementation in VHDL (targeting FPGAs) of the G-EDF multiprocessor scheduling policy.
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