Article Dans Une Revue Integration, the VLSI Journal Année : 2007

A fast pipelined multi-mode DES architecture operating in IP representation

Résumé

The Data Encryption Standard (DES) is a cipher that is still used in a broad range of applications, from smart- cards, where it is often implemented as a tamper-resistant embedded co-processor, to PCs, where it is implemented in software (for instance to compute crypt(3) on UNIX platforms.) To the authors’ knowledge, implementations of DES published so far are based on the straightforward ap- plication of the NIST standard. This article describes an innovative architecture that features a speed increase for both hardware and software implementations, compared to the state-of-the-art. For example, the proposed architec- ture, at constant size, is about twice as fast as the state- of-the-art for 3DES-CBC. The first contribution of this ar- ticle is an hardware architecture that minimizes the com- putation time overhead caused by key and message loading. The second contribution is an optimal chaining of computa- tions, typically required when “operation modes” are used. The optimization is made possible by a novel computation paradigm, called “IP representation”.

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hal-05273396 , version 1 (23-09-2025)

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Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet. A fast pipelined multi-mode DES architecture operating in IP representation. Integration, the VLSI Journal, 2007, 40 (4), pp.479-489. ⟨10.1016/j.vlsi.2006.06.004⟩. ⟨hal-05273396⟩
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