In synchronous data transfer, both sender and receiver use a common clock signal for data transfer. The master sends data in a fixed, predefined sequence, assuming the slave is ready at the required time.
- No acknowledgement signals are used; instead, timing is controlled by the clock.
- The master may introduce delays to match the slave’s speed.
- Before transfer, the master selects the slave using an address or control signal.
In this timing diagram:
- Master places address on address bus
- Master activates READ signal
- Slave places data on data bus
- Data is read within one clock cycle
- No acknowledgement signal is used
Features
- Timing: In synchronous data transfer, the data transfer is synchronized with a common clock signal that is generated by the sending device and used by both the sending and receiving devices. This ensures that both devices are in sync and ready to receive or transmit data at the same time.
- Data Transfer Modes: Synchronous data transfer can be done using either the parallel or serial mode of data transfer. In parallel data transfer, multiple bits of data are transferred simultaneously, while in serial data transfer, data is transferred bit-by-bit using a single data line.
- Handshaking: Synchronous data transfer typically involves some form of handshaking between the sending and receiving devices to ensure that the data is transferred correctly. This can involve the use of signals such as Acknowledge (ACK) and Ready (RDY), which indicate that the receiving device is ready to receive or that the sending device has completed the transfer.
- Data Rate: The data transfer rate in synchronous data transfer is typically limited by the clock frequency and the number of bits that can be transferred in a single clock cycle. However, synchronous data transfer can be faster than asynchronous data transfer because there is no need to add extra bits for synchronization.
- Transmission Line: In synchronous data transfer, the transmission line used to transfer data must be properly designed and matched to the impedance of the devices to ensure that data is not lost due to reflections.
Advantages
- The design procedure is easy. The master does not wait for any acknowledgement signal from the slave, though the master waits for a time equal to the slave's response time.
- The slave does not generate an acknowledge signal, though it obeys the timing rules as per the protocol set by the master or system designer.
Disadvantages
- If a slow-speed unit is connected to a common bus, it can degrade the overall rate of transfer in the system.
- If the slave operates at a slow speed, the master will be idle for some time during data transfer and vice versa.