GATE || DIGITAL LOGIC || COMBINATIONAL CIRCUIT || PYQ (2010 TO 2025 )

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Question 1

Consider the following combinational function block involving four Boolean variables x, y, a, b where x, a, b are inputs and y is the output.   

C++ 
f(x,y,a,b)
{
    if(x is 1)y =a;
    else y=b;
}


Which one of the following digital logic blocks is the most suitable for implementing this function?  [GATE||2014||SET3||MCQ||1MARKS]


  • Full adder


  • Priority encoder

  • Multiplexer


  • Flip-flop


Question 2

The dual of a Boolean function F(x1, x2, ..., xn, +, ⋅, '), written as FD, is the same expression as that of F with + and ⋅ swapped. F is said to be self-dual if F = FD. The number of self-dual functions with n Boolean variables is: [GATE||2014||SET2||MCQ||1MARKS]


  • 2n

  • 2(n-1)

  • 22^n

  • 22^(n-1)

Question 3

The Boolean expression for the output 'f' of the multiplexer shown below is ? [GATE|| 2010|| MCQ||1 Mark]

unnamed


  • (P ⊕ Q ⊕ R)'

  • P ⊕ Q ⊕ R

  • P + Q + R

  • (P + Q + R)'

Question 4

The amount of ROM needed to implement a 4 bit multiplier is ? [GATE||2012|| MCQ|| 1 MARKS]


  • 64 bits

  • 128 bits

  • 1 Kbits

  • 2 Kbits


Question 5

In the following truth table, V = 1 if and only if the input is valid.

dl-pyq-11

What function does the truth table represent?  [GATE ||2013 || MCQ ||1 Mark]


  • Priority encoder

  • Decoder

  • Multiplexer

  • Demultiplexer

Question 6

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ____________. [GATE||2015||SET2||NAT||1MARKS]


  • 19.2


Question 7

Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _________. [GATE||2016||SET2||NAT||1MARKS]



  • -1

Question 8

Consider the two cascaded 2-to-1 multiplexers as shown in the figure.


unnamed12


The minimal sum of products form of the output X is [GATE||2016||SET1||MCQ||2MARKS]

  • P'Q' + PQR

  • P'Q + QR

  • PQ + P'Q'R

  • Q'R' + PQR

Question 9

When two 8-bit numbers A7...A0 and B7...B0 in 2’s complement representation (with A0 and B0 as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are S7...S0 and the carry bits are C7...C0. An overflow is said to have occurred if [GATE||2017||SET1||MCQ||1MARKS]



  • the carry bit C7 is 1

  • all the carry bits (C7,…,C0) are 1

  • (A7 . B7 . S7' + A7' . B7' . S7) is 1

  • (A0 . B0 . S0' + A0' . B0' . S0) is 1

Question 10

A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____. [GATE 2020|| NAT|| 2 marks]



  • 5

There are 15 questions to complete.

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