Question 1
Consider Z = X - Y, where X, Y and Z are all in sign-magnitude form. X and Y are each represented in n bits. To avoid overflow, the representation of Z would require a minimum of: [GATE 2019 || MCQ ||1 Mark ]
n bits
n + 2 bits
n - 1 bits
n + 1 bits
Question 2
Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1+R2, which one of the following values of R1 and R2 gives an arithmetic overflow? [GATE|| 2022 MCQ || 2-mark ]
R1 = 1011 and R2 = 1110
R1 = 1100 and R2 = 1010
R1 = 0011 and R2 =0100
R1 = 1001 and R2 = 1111
Question 3
Consider three floating point numbers A, B and C stored in registers RA , RB and RC respectively as per IEEE-754 single precision floating point format. The 32-bit content stored in these registers (in hexadecimal form) are as follows.
RA=0xC1400000
RB=0x42100000
RC=0x41400000
Which one of the following is FALSE? [GATE || 2022 ||MCQ || 2-mark ]
A+C=0
C=A+B
B=3C
(B−C)>0
Question 4
A particular number is written as 132 in radix-4 representation. The same number in radix-5 representation is _____. [GATE || 2023 NAT || 1-mark]
110
Question 5
Consider the IEEE-754 single precision floating point numbers P=0xC1800000 and Q=0x3F5C2EF4.
Which one of the following corresponds to the product of these numbers (i.e., P x Q), represented in the IEEE-754 single precision format? [GATE|| 2023 ||MCQ ||1-mark ]
0x404C2EF4
0x405C2EF4
0xC15C2EF4
0xC14C2EF4
Question 6
Which of the following is/are EQUAL to 224 in radix-5 (i.e., base-5) notation ? [GATE||2024 ||SET2||MSQ ||1-mark ]
64 in radix-10
100 in radix-8
50 in radix-16
121 in radix-7
Question 7
Consider a system that uses 5 bits for representing signed integers in 2's complement format. In this system, two integers A and B are represented as A=01010 and B=11010 . Which one of the following operations will result in either an arithmetic overflow or an arithmetic underflow? [GATE||2024 ||SET-1||MCQ ||1-mark ]
A + B
A - B
B - A
2 * B
Question 8
he format of a single-precision floating-point number as per the IEEE 754 standard is:
Sign (1 bit) | Exponent (8 bits) | Mantissa (23 bits) |
Choose the largest floating-point number among the following options. [GATE || 2024||SET2|| MCQ ||1-mark ]
Sign - 0
Exponent - 0111 1111
Mantissa - 23 0’s
Sign - 0
Exponent - 0111 1111
Mantissa - 23 1’s
Sign - 0
Exponent - 111 11110
Mantissa - 23 1’s
Sign - 0
Exponent - 1111 1111
Mantissa - 23 1’s
Question 9
The following two signed 2's complement numbers (multiplicand M and multiplier Q are being multiplied using Booth's algorithm:
M: 1100110111101101 and Q: 1010010010101010
The total number of addition and subtraction operations to be performed is _______ [GATE ||2025 SET2 || NAT || 2-mark]
13
Question 10
The number −6 can be represented as 1010 in 4-bit 2's complement representation. Which of the following is/are CORRECT 2's complement representation(s) of −6 ? [GATE|| 2025 SET1||MSQ ||1-mark]
1000 1010 in 8 bits
1111 1010 in 8 bits
1000 0000 0000 1010 in 16 bits
1111 1111 1111 1010 in 16 bits
There are 24 questions to complete.