GATE || DIGITAL ELECTRONICS / LOGIC ||PYQ (2010 TO2025)

The above synchronous sequential circuit built using JK flip-flops is initialized with Q2Q1Q0=000. The state sequence for this circuit for the next 3 clock cycles is: [GATE||2014||SET3||MCQ||2MARKS]

In a 4-bit ripple counter, if the period of the waveform at the last flip-flop is 64 microseconds, then the frequency of the ripple counter in kHz is ________. (Answer in integer) [GATE|| 2025 ||SET 2 || NAT || 2-mark]

Consider the given sequential circuit designed using D-Flip-flops. The circuit is initialized with some value (initial state). The number of distinct states the circuit will go through before returning back to the initial state is _________. (Answer in integer) [GATE||2025 ||SET1 ||NAT ||2 MARKS]

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.

The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ______[GATE 2018||NAT|| 1 Mark]

Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.

Initially, both Q₀ and Q₁ are set to 1 (before the 1^st clock cycle). The outputs [GATE 2017|| SET1 || MCQ||2 Marks]

The next state table of a 2-bit saturating up-counter is given below.

The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for T₁ and T₀ are [GATE 2017 ||SET 2||MCQ||2 Marks]

We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is __________. [GATE||2016||SET1||NAT||1MARKS]

A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays. [GATE||2015||SET1||MCQ||2MARKS]

Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is [GATE||2015||SET1||MCQ||1MARKS]

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,…….) is ___________. [GATE||2015||SET2||NAT||1MARKS]