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GATE EC || DIGITAL LOGIC || FSM || PYQS(2000-2025)
Question 1
The state diagram of a sequence detector is shown below. State S₀ is the initial state of the sequence detector. If the output is 1, then
(GATE 2020 || EC || PYQ || MCQ ||2 MARK)
The sequence 01010 is detected.
The sequence 01011 is detected.
The sequence 01110 is detected.
The sequence 01001 is detected.
Question 2
The state transition diagram for the circuit shown is
( GATE 2019 || EC || PYQ || MCQ ||2 MARK)
Question 3
In the circuit shown, what are the values of F for EN = 0 and EN = 1, respectively?
( GATE 2019 || EC || PYQ || MCQ ||2 MARK)
0 and 1
Hi – Z and D̅
0 and D
Hi –Z and D
Question 4
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S0,
If the input sequence 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is ____
( GATE 2017 || EC || PYQ || MCQ ||2 MARK)
4
Question 5
A finite state machine (FSM) is implemented using the D flip-flops A and B and logic gates, as shown in the figure below. The four possible states of the FSM are QAQB = 00, 01, 10, and11.
Assume that XIN is held at constant logic level throughout the operation of the FSM. When the FSM is initialized to the QAQB = 00 and clocked, after a few clock cycles, it starts cycling through
( GATE 2017 || EC || PYQ || MCQ ||2 MARK)
all of the four possible states if XIN = 1.
three of the four possible states if XIN = 0.
Only two of the four possible states if XIN = 1.
only two of the four possible states if XIN = 0.
Question 6
The state transition diagram for a finite state machine with states A. B and C, and binary inputs X, Y and Z, is shown in the figure. Which one of the following statements is correct?
( GATE 2016 || EC || PYQ || MCQ || 1 MARK)
Transitions from State A are ambiguously defined
Transitions from State B are ambiguously defined.
Transitions from State C are ambiguously defined.
All of the state transitions are defined unambiguously
Question 7
The state transition diagram for the logic circuit shown in
( GATE 2012 || EC || PYQ || MCQ ||2 MARK)
Question 8
A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN, in each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds, and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this FSM is a clock of 5 second period. The minimum number of flip-flops required to implement this FSM is ……….
( GATE 2018 || EC || PYQ || NAT ||1 MARK)
5
There are 8 questions to complete.