GATE EC || DIGITAL LOGIC || SEQUENTIAL CIRCUIT || PYQS (2000-2025)

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns, and that of the counter is assumed to be zero.

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

( GATE 2015 || EC || MCQ || 1 MARK )

Five JK flip-flops are cascaded to form the circuit shown in the figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q₃ is:

( GATE 2014 || EC || MCQ || 1 MARK )

In the circuit shown, choose the correct timing diagram of the output (Y) from the given waveforms W₁, W₂, W₃ and W₄

(GATE 2014 || EC || MCQ ||1 MARK)

The outputs of the two flip-flops Q₁, Q₂ in the figure shown are initialized to 0, 0. The sequence generated at Q₁ upon application of clock signal is

(GATE 2014 || EC || MCQ || 1 MARK)

A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of n is: ( GATE 2014 || EC || NAT || 1 MARK )

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

(GATE 2015 || EC || MCQ || 1 MARK)

An SR latch is implemented using TTL gates, as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing

(GATE 2015 || EC || MCQ || 1 MARK)

A three-bit pseudo-random number generator is shown. Initially, the value of output Y = Y₂Y₁Y₀ is set to 111. The value of output Y after three clock cycles is

( GATE 2015 || EC || MCQ || 1 MARK)