GATE EC || ELECTRONICDEVICES AND CIRCUIT || MOS CAPACITOR || PYQS (2000-2025)

A MOS capacitor made using p-type substrate is in the accumulation mode. The dominant charge in the channel is due to the presence of  

(GATE 2005|| EC || MCQ ||1 MARK)

The figure shows the high-frequency capacitance-voltage (C-V) characteristics of a Metals/SiO₂/silicon (MOS) capacitor having an area of 1 × 10⁻⁴ cm². Assume that the permittivities (ε₀εᵣ) of silicon and SiO₂ are 1 × 10⁻¹² F/cm and 3.5 × 10⁻¹³ F/cm respectively. The gate oxide thickness in the MOS capacitor is 

(GATE 2007 || EC || MCQ|| 2 MARK)

The figure shows the high-frequency capacitance–voltage (C–V) characteristics of a [Tex]\text{Metal/SiO}_2\text{/Silicon (MOS)}[/Tex] capacitor having an area of [Tex]1 \times 10^{-4}\ \text{cm}^2[/Tex]. Assume that the permitivities [Tex](\varepsilon_0 \varepsilon_r)[/Tex] of silicon and [Tex]\text{SiO}_2[/Tex] are [Tex]1 \times 10^{-12}\ \text{F/cm} \quad \text{and} \quad 3.5 \times 10^{-13}\ \text{F/cm}[/Tex], respectively.

The maximum depletion layer width in Silicon is

(GATE 2007 || EC || MCQ || 2 MARK)

In the three-dimensional view of a silicon n-channel MOS transistor shown below, δ=20nm. The transistor has a width of 1μm. The depletion width formed at every p–n junction is 10nm. The relative permitivities of Si and [Tex]\text{SiO}_2[/Tex] are 11.7 and 3.9, respectively, and [Tex]\varepsilon_0 = 8.9 \times 10^{-12}\ \text{F/m}[/Tex]

The source-body junction capacitance is approximately

(GATE 2022 || EC || MCQ || 1 MARK)

An ideal MOS capacitor has boron doping concentration of 10¹⁵ cm^–3 in the substrate. When a gate voltage is applied, a depletion region of width 0.5 μm is formed with a surface (channel) potential of 0.2 V. 

Given that ε₀ = 8.854 × 10^–14 F/cm and the relative permittivity’s of silicon and silicon dioxide are 12 and 4, respectively, the peak electric field (in V/μm) in the oxide region is ____.  

(GATE 2014 || EC || NAT||1 MARK)

In a MOS capacitor with an oxide layer thickness of 10 nm, the maximum depletion layer thickness is 100 nm. The permittivities of the semiconductor and the oxide layer are 𝜀_𝑠 and 𝜀_𝑂𝑆 respectively. Assuming 𝜀_𝑠/𝜀_𝑂𝑋 = 3, the ratio of the maximum capacitance to the minimum capacitance of this MOS capacitor is.

(GATE 2014 || EC || NAT||1 MARK)

The figure shows the band diagram of a Metal Oxide Semiconductor (MOS). The surface region of this MOS is in

(GATE 2016|| EC || MCQ || 1 MARK)

Figure I and II show two MOS capacitors of unit area. The capacitor in Figure I has insulator materials X (of thickness t₁ = 1 nm and dielectric constant ε₁ = 4) and Y (of thickness t₂ = 3 nm and dielectric constant ε₂ = 20). The capacitor in Figure II has only insulator material X of thickness t_eq. If the capacitors are of equal capacitances, then the value of t_Eq (in nm) is _____.

(GATE 2016|| EC || MCQ ||1 MARK)

A voltage V_G is applied across a MOS capacitor with metal gate and p-type Silicon substrate at T = 300 K. The inversion carrier density (in number of carriers per unit area) for V_G = 0.8 V is 2 × 10¹¹ cm^–2. For V_G = 1.3 V, the inversion carrier density is 4 × 10¹¹ cm^–2. For V_G = 1.3 V, the inversion carrier density is 4 × 10¹¹cm^–2. What is the value of the inversion carrier density for V_G = 1.8 V?  

(GATE 2016 || EC || MCQ || 2 MARK)

The band diagram of a p-type semiconductor with a band -gap of 1eV is shown, using this semiconductor, a MOS capacitor having V_th of -0.16 V, C’_ox of 100 nF/cm² and a metal work function of 3.87 eV is fabricated. There is no charge within the oxide. If the voltage across the capacitor is V_TH, the magnitude of depletion charge per unit area (in C/cm²) is

(GATE 2020 || EC || MCQ || 2 MARK)