In the circuit shown in the figure, the transistors M1 and M2 are operating in saturation. The channel length modulation coefficients of both the transistors are non-zero. The transconductance of the MOSFETs M1 and M2 are gm1 and gm2 respectively and internal resistance of MOSFETS M1 and M2 are r01 and r02, respectively. Ignoring the body effect, the ac small signal gain (∂Vout/∂Vin) of the circuit is(GATE 2021 || EC || PYQ || MCQ || 1 MARKS)

$$-g_{m2} left( frac{1}{g_{m1}} parallel r_{o1} parallel r_{o2} ight)$$

$$-g_{m2}(r_{o1} parallel r_{o2})$$

$$-g_{m2} left( frac{1}{g_{m1}} parallel r_{o2} ight)$$

$$-g_{m1} left( frac{1}{g_{m2}} parallel r_{o1} parallel r_{o2} ight)$$

GATE EC||ANALOG ELECTRONIC||MOS||PYQS(2000-2025)

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Question 1

For the n-channel MOS transistor shown in the figure, the threshold voltage V_th is 0.8 V. Neglect channel length modulation effects. When the drain voltage V_D = 1.6 V, the drain current I_D was found to be 0.5 mA. If V_D is adjusted to be 2 V by changing the values of R and V_DD, the new value of I_D (in mA) is

( GATE 2014 || EC || PYQ || MCQ || 2 MARKS)

0.625
0.75
1.125
1.5

Question 2

For the transistor M₁ in the circuit shown in the figure, μ_nC_OX = 100μA/V² and (W/L) = 10, where μ_n is the mobility of electron. C_OX is the oxide capacitance per unit area. W is the width and L is the length.

The channel length modulation coefficient is ignored. If the gate-to-source voltage V_GS is 1V to keep the transistor at the edge of saturation, then the threshold voltage of the transistor (rounded off to one decimal place) is_____ V.

( GATE 2021 || EC || PYQ || NAT||2 MARKS)

0.5V

Question 3

In the circuit shown in the figure, the transistors M₁ and M₂ are operating in saturation. The channel length modulation coefficients of both the transistors are non-zero. The transconductance of the MOSFETs M₁ and M₂ are g_m1 and g_m2 respectively and internal resistance of MOSFETS M₁ and M₂are r₀₁ and r₀₂, respectively.

Ignoring the body effect, the ac small signal gain (∂V_out/∂V_in) of the circuit is

(GATE 2021 || EC || PYQ || MCQ || 1 MARKS)

[Tex]-g_{m2}(r_{o1} \parallel r_{o2})[/Tex]
[Tex]-g_{m2}\left(\frac{1}{g_{m1}} \parallel r_{o1} \parallel r_{o2}\right)[/Tex]
[Tex]-g_{m2}\left(\frac{1}{g_{m1}} \parallel r_{o2}\right)[/Tex]
[Tex]-g_{m1}\left(\frac{1}{g_{m2}} \parallel r_{o1} \parallel r_{o2}\right)[/Tex]

Question 4

Using the incremental low frequency small-signal model of the MOS device, the Norton equivalent resistance of the following circuit is

(GATE 2020 || EC || PYQ || MCQ || 2 MARKS)

[Tex]r_{ds} + R + g_m r_{ds}R[/Tex]
[Tex]\frac{r_{ds} + R}{1 + g_m r_{ds}}[/Tex]
[Tex]r_{ds} + R[/Tex]
[Tex]r_{ds} + \frac{1}{g_m} + R[/Tex]

Question 5

An enhancement MOSFET of threshold voltage 3V is being used in the sample and hold circuit given below. Assume that the substrate of MOS device is connected to –10V. If the input voltage V₁ lies between ± 10V, the minimum and the maximum values of V_G required of proper sampling and holding respectively, are

(GATE 2020 || EC || PYQ || MCQ || 2 MARKS)

10 V and -10 V
10 V and -13 V
13 V and -7V
3V and -3V

Question 6

(GATE 2019 || EC || PYQ || NAT ||2 MARKS)

–900

Question 7

(GATE 2017 || EC || PYQ || NAT ||2 MARKS)

0.225

Question 8

(GATE 2018 || EC || PYQ || MCQ ||1 MARKS)

g_m = g_m1. g_m2. r₀₂ and r₀ = r₀₁ + r₀₂
g_m = g_m1 + g_m2 and r₀ = +r₀₂
g_m = g_m1 and r₀= r₀₁. g_m2. r₀₂
g_m = g_m1 and r₀ = r₀₂

Question 9

An n-channel enhancement mode MOSFET is biased at V_GS > V_TH and V_DS > (V_GS - V_TH), where V_GS is the gate-to-source voltage. V_DS is the drain-to-source voltage and V_TH is the threshold voltage. Considering channel length modulation effect to be significant, the MOSFET behaves as a

(GATE 2017 || EC || PYQ || MCQ ||1 MARKS)

voltage source with zero output impedance
voltage source with non-zero output impedance
current source with finite output impedance
current source with infinite output impedance

Question 10

In the circuit shown in the figure, the channel length modulation of all transistor is non-zero Also, all transistors operate in saturation and have negligible body effect. The ac small signal voltage gain (V₀/V_in) of the circuit is

(GATE 2016 || EC || PYQ || MCQ || 2 MARKS)

[Tex]-g_{m1}(r_{o1} \parallel r_{o2} \parallel r_{o3})[/Tex]
[Tex]-g_{m1}\left(r_{o1} \parallel \frac{1}{g_{m3}} \parallel r_{o3}\right)[/Tex]
[Tex]-g_{m1}\left(r_{o1} \parallel \left(\frac{1}{g_{m2}} \parallel r_{o2}\right) \parallel r_{o3}\right)[/Tex]
[Tex]-g_{m1}\left(r_{o1} \parallel \left(\frac{1}{g_{m2}} \parallel r_{o3}\right) \parallel r_{o2}\right)[/Tex]

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