GATE||COA|| Pipelining and Secondary Memory || Pyqs (2010 to 2025 )

The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is _________ bits.
[GATE 2016 || SET-2 NAT || 2 marks]

An application loads 100 libraries at start-up. Loading each library requires exactly one disk access. The seek time of the disk to a random location is given as 10 ms. Rotational speed of disk is 6000 rpm. If all 100 libraries are loaded from random locations on the disk, how long does it take to load all libraries? (The time to transfer data from the disk block once the head has been positioned at the start of the block may be neglected)
[GATE 2011 || MCQ || 2-mark]

An instruction pipeline has five stages, namely:

1. Instruction Fetch (IF) – latency = 1 ns
2. Instruction Decode and Register Fetch (ID/RF) – latency = 2.2 ns
3. Instruction Execution (EX) – latency = 2 ns
4. Memory Access (MEM) – latency = 1 ns
5. Register Write Back (WB) – latency = 0.75 ns

(ns stands for nanoseconds).

To gain in terms of frequency, the designers have decided to:

• Split the ID/RF stage into three stages (ID, RF1, RF2) each of latency:

2.2/3 ns ≈ 0.73ns

• Split the EX stage into two stages (EX1, EX2) each of latency 1 ns.

Thus, the new design has a total of 8 pipeline stages.

A program has 20% branch instructions, which execute in the EX stage and produce the next instruction pointer:

• At the end of the EX stage in the old design.
• At the end of the EX2 stage in the new design.

The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed.

• All instructions other than branch instructions have an average CPI = 1 in both designs.
• The execution times of this program on the old and the new design are P and Q nanoseconds, respectively.

The value of  Q/P​ = ?
[GATE 2014 || SET-3 MCQ || 2 marks]

A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below:

• Block size in L1 cache: 4 words
• Block size in L2 cache: 16 words
• Memory access times:
  • L1 cache: 2 nanoseconds
  • L2 cache: 20 nanoseconds
  • Main memory: 200 nanoseconds

If there is a miss in the L1 cache and a hit in the L2 cache, a block is transferred from the L2 cache to the L1 cache.

What is the time taken for this transfer?
[GATE 2010 || MCQ || 2 marks]

An 8 KB direct-mapped write-back cache is organized as multiple blocks, each of size 32 bytes. The processor generates 32-bit addresses.

The cache controller maintains the tag information for each cache block, which includes:

1. 1 Valid bit
2. 1 Modified (dirty) bit
3. As many tag bits as required to uniquely identify the memory block mapped to the cache
   What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?
   [GATE 2011 || MCQ || 2 marks]

A computer has a 256 KByte, 4-way set associative, write-back data cache with a block size of 32 Bytes. The processor sends 32-bit addresses to the cache controller. Each cache tag directory entry contains, in addition to the address tag, 2 valid bits, 1 modified bit, and 1 replacement bit.
What is the number of bits in the tag field of an address?
[GATE 2012 || MCQ || 2 marks]

A computer has a 256 KByte, 4-way set associative, write-back data cache with a block size of 32 Bytes. The processor sends 32-bit addresses to the cache controller. Each cache tag directory entry contains, in addition to the address tag, 2 valid bits, 1 modified bit, and 1 replacement bit.

The number of bits in the tag field of an address is _________.
[GATE 2012|| MCQ || 2 marks]

A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8).
The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is ___ .
[GATE 2013 || MCQ || 2 marks]

In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are replaced in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from
[GATE 2013|| MCQ || 1 marks]

If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
[GATE 2014|| SET-2 MCQ || 2 marks]