GATE||COA||Instruction & Adressing mode || Pyq(2010 to 2025 )

Consider evaluating the following expression tree on a machine with load-store architecture in which memory can be accessed only through load and store instructions. The variables a, b, c, d and e are initially stored in memory. The binary operators used in this expression tree can be evaluated by the machine only when the operands are in registers. The instructions produce result only in a register. If no intermediate results can be stored in memory, what is the minimum number of registers needed to evaluate this expression?

[GATE 2011 || MCQ || 2-mark]

The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A15 to A0. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

[GATE 2019|| MCQ || 1-mark]

The program below uses six temporary variables a, b, c, d, e, f. 

   a = 1
    b = 10
    c = 20
    d = a+b
    e = c+d
    f = c+e
    b = c+e
    e = b+f
    d = 5+e
    return d+f

Assuming that all operations take their operands from registers, what is the minimum number of registers needed to execute this program without spilling?
[GATE 2010 MCQ || 2-mark]

The amount of ROM needed to implement at 4 bit multiplier is
[GATE 2012 MCQ || 1-mark ]

The format of a single-precision floating-point number as per the IEEE 754 standard is:

Choose the largest floating-point number among the following options.
[GATE 2024|| SET-2 MCQ || 2-mark ]

The value of a float type variable is represented using the single-precision 32-bit floating point format IEEE-754 standard that uses 1 bit for sign, 8 bits for biased exponent and 23 bits for mantissa. A float type variable X is assigned the decimal value of −14.25. The representation of X in hexadecimal notation is
[GATE 2014 || SET-2 MCQ || 2-mark]

Consider the IEEE-754 single precision floating point numbers P=0xC1800000 and Q=0x3F5C2EF4. Which one of the following corresponds to the product of these numbers (i.e., P × Q), represented in the IEEE-754 single precision format? [GATE 2023 || MCQ || 2-mark]

Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for operand in memory?
[GATE 2011 MCQ || 1-mark]

Consider the C struct defines below:

struct data { 
    int marks [100] ; 
    char grade; 
    int cnumber; 
};
 
struct data student; 

The base address of

student

is available in register R1. The field

student.grade

can be accessed efficiently using
[GATE 2017|| SET-1 MCQ || 1-mark]

Consider the following instruction sequence where registers R1, R2 and R3 are general purpose and MEMORY [X] denotes the content at the memory location X.

Assume that the content of the memory location 5000 is 10, and the content of the register R3R3​ is 3000. The content of each of the memory locations from 3000 to 3020 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable.
After the execution of the program, the content of memory location 3010 is ____________?
[GATE 2021 || SET-1 NAT || 2-mark]