EE141-Fall 2003 Digital Integrated Circuits

Lecture 24 Sequential Logic

EE141 EECS141

Midterm 2
Hi:

39 (Grad: 40) Lo: 7 Median (UG) : 26 Distribution is bimodal, groups around 30 and around 20.

EE141 EECS141

Administrative Stuff
Homework

8 due next Thursday Project phase 3 is this week, report due next Tuesday Please turn in your lab 6 reports by this Fridays discussion (if you want any credit for them

EE141 EECS141

Class Material
Last

lecture

Hardware description languages Introduction to sequential logic

Todays

lecture

Sequential logic: latches and registers

EE141 EECS141

Sequential Logic

EE141 EECS141

Positive Feedback: Bi-Stability

Vi 1 V o1 = V i 2 V o2

V o1
1 o V

Vi2
V 5

V o2 = V i 1
2 i

V i1 A
1

V o2

V i 2 = V o1
o V 5 2 i

C B V i 1 = V o2

EE141 EECS141

Meta-Stability
V i 2 5 V o1 V i 2 5 V o1
C A A

B
d

B
d

V i 1 5 V o2

V i 1 5 V o2

Gain should be larger than 1 in the transition region

7

EE141 EECS141

Writing into a Static Latch

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
CLK

CLK
Q CLK

D CLK

CLK

Converting into a MUX

Forcing the state (can implement as NMOS-only)

8

EE141 EECS141

Cross-Coupled Pairs
NOR-based set-reset
S S Q S R R Q Q Q 0 1 0 1 Forbidden State 0 0 1 1 Q 1 0 0 Q 0 1 0 R Q Q

The Overpowering Approach

EE141 EECS141

Cross-Coupled NAND
Cross-coupled NANDs
S

Added clock
VDD M2 Q M4 Q

CLK

M6 M5

M1

M3

M8 M7

CLK

This is not used in datapaths any more, but is a basic building memory cell
EE141 EECS141

10

Sizing Issues
2.0 1.5 3 Q 2 1.0 0.5 0.0 2.0 0 W = 1 m S W = 0.5 m W = 0.6 m W = 0.7 m 1 W = 0.8 m W = 0.9 m

Q (Volts)

2.5

3.0 W/L 5 and 6 (a)

3.5

4.0

Volts

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ns) (b)

Output voltage dependence on transistor width EE141 EECS141

Transient response

11

Master-Slave (Edge-Triggered) Register

Slave Master 0 1 D 0 QM 1 CLK Q D QM Q CLK CLK

Two opposite latches trigger on edge Also called master-slave latch pair
EE141 EECS141

12

Master-Slave Register
Multiplexer-based latch pair

I2

T2

I3 QM

I5

T4

I6

I1

T1

I4

T3

CLK

EE141 EECS141

13

Clk-Q Delay
2.5

CLK
Volts
1.5 D

tc q(lh) Q

tc q(hl)

0.5

0.5

0.5

1 1.5 time, nsec

2.5

EE141 EECS141

14

Setup Time
3.0 2.5 2.0 Q QM CLK I2 T2 3.0 2.5 2.0

I2 T2
D CLK QM Q

Volts

D 1.0 0.5 0.0 0.5 0

Volts
0.6 0.4 time (nsec) 0.8 1

1.5

1.5 1.0 0.5 0.0

0.2

0.5

0.2

0.6 0.4 time (nsec)

0.8

(a) Tsetup 0.21 nsec

(b) Tsetup 0.20 nsec

15

EE141 EECS141

Reduced Clock Load Master-Slave Register

CLK D CLK

T1 CLK

I1 I2

T2 CLK

I3 I4

EE141 EECS141

16

Avoiding Clock Overlap

CLK A B X CLK Q D

CLK (a) Schematic diagram

CLK

CLK

CLK (b) Overlapping clock pairs

EE141 EECS141

17

More Precise Setup Time

Clk t D t Q t (a)

1.05tC Q

tC Q

tSu tH
EE141 EECS141

tD C

(b)

18

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2 D1 Inv1 SM

QM

Clk-Q Delay

CP
TClk-Q TSetup-1
Time

Data

TSetup-1
t=0

Clock

Time

EE141 EECS141

19

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2 D1 Inv1 SM

QM

Clk-Q Delay

CP
TClk-Q TSetup-1
Time

Data

TSetup-1
t=0

Clock

Time

EE141 EECS141

20

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2 D1 Inv1 SM

QM

Clk-Q Delay

CP

TClk-Q

TSetup-1

Time

Data

TSetup-1
t=0

Clock

Time

EE141 EECS141

21

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

TClk-Q

CP

TSetup-1

Time

Data TSetup-1
t=0 EE141 EECS141

Clock

Time

22

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)
CN
TG1 Inv2
Clk-Q Delay TClk-Q

D
Inv1

D1

SM

QM

CP

TSetup-1

Time

Data

Clock TSetup-1
t=0 Time

EE141 EECS141

23

Setup-Hold Time Illustrations

Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

CP

0
TClk-Q THold-1

Time

Clock THold-1
t=0

Data

Time

EE141 EECS141

24

Setup-Hold Time Illustrations

Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

CP

0
TClk-Q THold-1

Time

Clock THold-1
t=0 EE141 EECS141

Data

Time

25

Setup-Hold Time Illustrations

Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

CP

TClk-Q

THold-1

Time

Clock THold-1
t=0 EE141 EECS141

Data

Time

26

Setup-Hold Time Illustrations

Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

TClk-Q

CP

THold-1

Time

Clock THold-1
t=0 EE141 EECS141

Data

Time

27

Setup-Hold Time Illustrations

Hold-1 case
CN
TG1 Inv2
Clk-Q Delay

D
Inv1

D1

SM

QM

TClk-Q

CP

THold-1

Time

Clock

Data THold-1
t=0 Time

28

EE141 EECS141

Other Latches/Registers: C2MOS

VDD M2 CLK D CLK M3 M1 M4 X C L1 CLK M7 M5 CLK VDD M6 M8 Q C L2

Master Stage
EE141 EECS141

Slave Stage
29

Keepers can be added to staticize

Other Latches/Registers: TSPC

VDD VDD VDD VDD

Out In CLK CLK In CLK CLK Out

EE141 EECS141

Positive latch Negative latch (transparent when CLK= 1) (transparent when CLK= 0) 30

Including Logic in TSPC

VDD PUN Q In CLK CLK CLK CLK VDD In1 VDD In2 Q VDD

PDN

In1

In2

Example: logic inside the latch

EE141 EECS141

AND latch

31

TSPC Register
VDD M3 CLK VDD M6 Y D CLK M2 X M5 CLK M8 VDD M9 Q Q

M1

CLK

M4

M7

EE141 EECS141

32

Pulse-Triggered Latches
Ways to design an edge-triggered sequential cell:
Master-Slave Latches
Data

Pulse-Triggered Latch L2
D Q Clk Data Clk

L1
D Q Clk

L
D Q Clk

Clk

EE141 EECS141

33

Pulsed Latches
VDD M3 VDD M6 Q D CLKG M2 CLKG M5 MP X CLKG CLK VDD

M1

M4

MN

(a) register

(b) glitch generation

CLK CLKG (c) glitch clock

EE141 EECS141

34

Pulsed Latches
Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 :
CLK P1 M3 D M2 M1 P2 P3 M6 M5 M4

CLKD

EE141 EECS141

35

HLFF Timing
3.0 2.5 2.0
Volts

1.5 1.0 0.5 0.0 20.5 0.0 0.2 0.4 0.6 time (ns) 0.8 1.0
36

CLK

CLKD

EE141 EECS141

Pipelining
REG
a
a

REG

REG

REG

REG

REG
CLK

CLK

log

Out
b

CLK

log

Out

REG

REG

CLK

CLK

CLK

CLK

CLK

Reference

Pipelined

EE141 EECS141

37

Latch-Based Pipeline
CLK In C1 CLK CLK Out C3

F C2

CLK CLK

Compute F
EE141 EECS141

compute G
38

Other Sequential Circuits

Schmitt

Trigger Monostable Multivibrators Astable Multivibrators

EE141 EECS141

39

Schmitt Trigger
In Out

Vou t

V OH

VTC with hysteresis Restores signal slopes

V OL

VM
EE141 EECS141

VM+

Vi n
40

Noise Suppression using Schmitt Trigger

Vin VM+ Vout

VM t0 t t0 + tp t

EE141 EECS141

41

CMOS Schmitt Trigger

VDD

M2 Vin M1 X

M4 Vout M3

Moves switching threshold of the first inverter

EE141 EECS141

42

Schmitt Trigger Simulated VTC

2.5 2.0 1.5
) V ( X V

2.5 2.0 VM1

) V ( x

1.5
V

1.0 0.5 0.0 0.0

VM2

1.0 0.5 0.0 0.0

k=1 k=2

k=3 k=4

0.5

1.0 1.5 Vin (V)

2.0

2.5

0.5

1.0 1.5 Vin (V)

2.0

2.5

Voltage-transfer characteristics with hysteresis.

The effect of varying the ratio of the PMOS device M4. The width is k* 0.5 m. 43

EE141 EECS141

CMOS Schmitt Trigger (2)

VDD M4 M6 M3 In M2 X M1
EE141 EECS141

Out

M5

VDD

44

Multivibrator Circuits
R S Bistable Multivibrator flip-flop, Schmitt Trigger

T Monostable Multivibrator one-shot

Astable Multivibrator oscillator

EE141 EECS141

45

Transition-Triggered Monostable

In

DELAY td

Out td

EE141 EECS141

46

Monostable Trigger (RC-based)

VDD In R A C B Out (a) Trigger circuit.

In

VM

(b) Waveforms.

Out t1
EE141 EECS141

t t2

47

Astable Multivibrators (Oscillators)

0 1 2 N-1

Ring Oscillator
3.0 2.5 2.0 V1 V3 V5

Volts

1.5 1.0 0.5 0.0 20.5 0.0 0.5 time (ns) 1.0 1.5

simulated response of 5-stage oscillator

EE141 EECS141

48

Relaxation Oscillator
Out1 I1 I2 Out2

R Int

T = 2 (log3) RC
EE141 EECS141

49

Voltage Controller Oscillator (VCO)

VD D
M6

VDD
M4

Schmitt Trigger restores signal slopes

M2

In Iref Vcontr
M5 M1

Iref

M3

Current starved inverter

6 tpH L (nsec) 4 2

0.0 0.5

1.5

V co ntr (V)

2.5

propagation delay as a function of control voltage

EE141 EECS141

50

Next Lecture
Timing

EE141 EECS141

51