>) >) Fault Simulation Why Fault Simulation? . + Introduction 1. To evaluate the quality of a test set + Classical Fault Simulation - usually in terms of fault coverage 2. To incorporate into ATPG for test generation = due to its lower complexity 3. To construct fault di nary - for post-test diagnosis + Modern Fault Simulation for Combinational Circuits + Hardware Approaches to Fault Simul: Conceptual Fault Simulation Some Basics for Logic Simulation + For fault simulation purpose, mostly the gate delay is (scquences) aia assumed to be zero unless the delay faults are (Vectors) Faulty Circuit # (010) considered. Our main concern is the functional faults. Fy 2 + The logic values can be either two (0, 1) or three Faulty Circuit #2 (Bi) values (0, 1, X). For delay fault, more values will be : Detected? needed. Faulty Circuit # (AO) : . Fouttree Grout 4 + Two simulation mechanism: Primal Ah By | — Oblivious compiled-code: circuit is translated into Inputs | —-—"¢ ) )D program and all gates are executed for each pattern. (is) |__——"_T primary outputs (POs) — Interpretive event-driven: circuit structure and gate status are stored in the table and only those gates needed to be updated with a new pattern are processed SD) + Logic simulation on both good (fault-free) and faulty circOblivious Compiled Code SDE + Compiled codes - LDA A [load accumulator with value of A */ -AND B — /Mcalculate A and B*/ -AND C — Iealculate E=ABandC*/ -OR D__ frealculate Z=£ orD* = STA Z store result of Z*/ S\ Event-Driven + While (event list not empty) begin — t= next time in the list — for every event (i, ) begin + update value of gat tT schedule fanout gates of /in the event list if value changes are expected —end + end S\ Complexity of Fault Simulation Paul (F) franera)_ + Complexity = P * F *G~ 0(G}) with single s-a faults * The complexity is higher than logle simulation, 0(G?), but is much lower than test pattern generation, + In reality, the complexity is much lower due to fault, dropping and advanced techniques. Characteristics of Fault Simulation + Fault activity with respect to fault-free circuit is often sparse both in time and in space. + For example, F1 is not activated by the given pattern, while F2 affects only the lower part of this circuit, ° —-pP FA(s-2-0) F2(s-2-0) 1 —D* The efficiency of a fault simulator depends on its ability to exploit these characteristics.S\ Classical Fault Simulation Techniques + Common Characteri: St — In general, no restriction on the circuit types. — Developed before VLSI era. + Serial Fault Simulation — trivial single-fault single-pattern * Parallel Fault Simulation + Deductive Fault Simulation + Concurrent Fault Simulation S\ Parallel Fault Simulation + Taking advantage of inherent parallel operation of computer words to simulate faulty circuits in parallel with fault-free circuit — the number of faulty circuits, or faults, can be processed parallelly is limited by the word length. + Straightforward and memory efficient + Some weaknesses: — An event, a value change, of a single fault or fault-free circuit leads to the computation of the entire word. — The fault-free logic simulation is repeated for the number of passes. ) Example of Parallel Fault Simulation + Consider three faults: B/I, F/0, and J/0 —Bit-space: [ 3/0 | Bil] F/O] FF | where FF = Fault-free Tit Deductive Fault Simulation + A list of faults associated with each line containing the identifier of each fault which produces a fault effect on this line. — Only the faults with fault effect, or difference w.r4. fault-free circuit, is retained in the list. + The propagation of such lists can be based on set operation derived the gate types and values. — The list update is performed with each new pattern, which is not efficient in computer. — The list may dynamically grow is size, which incurs memory explosion problem.Illustration of Fault List > Fault List Propagation Rule Propaga Let the gate G = F(A,B) with input lists La and Ls and output list Lc to be updated. If in the fault-free circuit, — the value of G is 0(1), use F(F-) — the value of gate input A is 0(1), replace A in logic expression by LA(LA-) and A- by LA- (La). Replace * by intersection and + by union. A Consider a two-input AND gate i ) =1, B=1, C=1 at fault-free, LA+ LB + {C/O} , B=0, C=0 at fault-free, Le =La-* Lp + {C/1} Case 3: A=0, B=0, C=0 at fault-free, Le =LA* Le +{C/1} /) Add G/1(G/0) to the list Le. Example of Deductive Simulation la Example of Deductive Simulation Ib + Consider 3 faults: B/1, F/0, and J/0 + Consider 3 faults: B/1, F/0, and J/0 Le=(B/1}, Lr ={F/0}, La=0 Le=Lo = {B/1} Le = {B/1}, LE=(B/1}Example of Deductive >» Simulation Ic + Consider 3 faults: B/1, F/0, and J/0 A 1 Eee, Go Le ={B/1}, LF ={F/0}, Le=Lp = {B/1}, Lo = {B/1}, LE= {B/1}, LH = (B/1, F/0} Example of Deductive > Simulation Id + Consider 3 faults: B/1, F/0, and J/0 LB={B/1}, LF={F/0}, Le=Lo = {B/1}, Lo = {B/1}, Le = {B/1}, LH = (B/1,F/0}, Lu = (F/0,J/0} /) Example of Deductive Simulation Il + When A changes from 1 to 0 Le ={B/1}, LF ={F/0}, Le=Lo = {B/1}, Le =0, Le = (B/1}, LH = {B/1,F/0}, Ls = {B/1,F/0,J/0} yy, Concurrent Fault Simula' + Each gate retains a list of fault copies each of which stores the status of a fault exhibiting difference from fault-free values. + Simulation mechanism is similar to the conceptual fault simulation except that only the dynamical difference w.r.t. fault-free circuit is retained. + Very versatile in circuit types and gate delays + Although theoretically all faults in a circuit can be processed in one pass, memory explosion problem restricts the fault number in each pass.Example of Concurrent > Concurrent Fault Simulation . , Simulation | + Consider 3 faults: B/1, F/0, and J/0 : updated by both logic event and fault events: O} Ls = {01_1, B/1:10_1, Ft }0_0, J/0:01_0} TS Example of Concurrent Simulation Il Modern Combinational Simulation Techniques + When A changes from 1 to 0 + Parallel pattern + Critical path tracing + Other sophisticated techniquesParallel-Pattern Single-Fault >) Propagation (PPSFP) + Many patterns are simulated in parallel for both fault-free and faulty circuits. The number of patterns is a multiple of computer word length. + Coincident logic events of fault-free circuit from these patterns can be simulated in parallel. — reduction of logic event simulation time + Coincident fault events of faulty circuits from these patterns can also be simulated in parallel. — reduction of fault event simulation time ple and extremely efficient — basis of all modern combinational fault SD) simulators Comparison with Parallel-Fault + Fault event maps for Parallel-pattern (upper) and parallel-fault (lower) + Parallel-Pattern case: Consider three patterns: P41, P2, P3. + Parallel-Fault case: Consider three faults: F1, F2, F3. + The overlapping of fault ‘events is inherently much higher in parallel-pattern simulation, and hence more event can be done at the same time, TS S\ Example of Parallel Pattern Simulation + Consider one fault F/0 and four patterns: P3,P2,P1,P0 —Bit-space:|P3 [P2 [1 Po] faulty value in red TT A i ctor [- e [0 Soe Tel o[t|ol1 ox [ TPpy) Toyo eyoyo Critical Path Tracing Two-step Procedure: — Fault-free simulation and identification of the sensitive gate inputs — Backtracing to identify the critical lines (critical path tracing) 0(G) complexity for fanout-free circuits ~- very rare in practice However, it becomes effecitve in fanout-free in when stem faults are simulated by parallel-pattern fault simulator.Basics of Cri ical Path Tracing Aline lis critical w.r.t. a pattern t iff t detects the fault /v. Paths of critical lines are critical paths. A gate input /is sensitive if complementing the value of / changes the value of the gate output. A gate input /is critical w.r-t. a pattern tif the gate output is critical and iis sensitive w.r-t. t. Ina fanout-free circuit, the criticality of all lines can be determined by backward traversing the successive sensitive gate inputs from POs, in linear time. S\ Example of Critical Path Tracing + sensitive input, — critical line (fanout-free region) Detected faults in the fanout-free region: {J/0, H/0, F/0, E/0, D/1} SD) Anomaly of Critical Path Tracing + Stem criticality is hard to infer from branches. E.g. is B/1 detectable by the given pattern? + It turns out B/1 is not detectable even though both C and D are critical, because its effects cancel each other out at gate J. + There is also multiple path sensitization problem. DS le Path Sensitization + sensitive input, —— critical line (stem) 7 (fanout-free region) Both C and D are not critical, yet B is critical and B/O can be detected at J by multiple path sensitization. SD)Other Sophisticated Techniques = in the right figure, dx) determined from its exit lines yf, y2, and y3 + Multiple Packet Simulation jory space to Improve spot + Selective or Demand-driven Fault-free Simulation ~ reduce unnecessary fault- free simulation as undetected faults become dx) = d(Ce-yt) diy1) + dey2) aly2) less ) + dlxy3)d(y3) Hardware Approaches to >) Fault Simulation + Commercialized Dedicated Accelerators: — IKOS & ZYCAD + Other Hardware Ideas — Associative Memory ~ Cellular Automata — Field-Programmable Gate Array Cellular Automata + The cellular automata is a 2D array of very simple processors with interconnection to 4 immediate neighbors. It can be regarded as a massively parallel pipelined computer. + [CA95] shows both gates and interconnects of a circuit can be mapped into the cellular automata and the CA can execute logic and fault si with additional comparison. + Mainly restricted to com! ulation nal circuits. Field Programmable Gate Array gate array mapped from any logic circuits and emulated much faster than software simulation. + The fault insertion process Is slow. One way to minimize the insertion is to have both good gates and faulty gates within FPGA as shown left [FPGA95]. ACLB with a dynamic fault Injected (activated with x=1) /)