Class 11: Transmission Gates, Latches

Topics:
1. Intro
2. Transmission Gate Logic Design
3. X-Gate 2-to-1 MUX
4. X-Gate XOR
5. X-Gate 8-to-1 MUX
6. X-Gate Logic Latch
7. Voltage Drop of n-CH X-Gates
8. n-CH Pass Transistors vs. CMOS X-Gates
9. n-CH Pass Transistors vs. CMOS X-Gates
10. Full Swing n-CH X-Gate Logic
11. Leakage Currents
12. Static CMOS Digital Latches
13. Static CMOS Digital Latches
14. Static CMOS Digital Latches
15. Static CMOS Digital Latches
Joseph A. Elias, PhD

Class 11: Transmission Gates, Latches

Transmission Gates (Martin, c5.1)
Pass Transistors, a.k.a., Transmission Gates are same as a relay
Why? Usually allows for a reduction in number of transistors

NMOS
Vcntl H
Out
In

L
Z

CMOS
Vcntl H
Vcntl L
Out
In

Joseph A. Elias, PhD

L
H
Z

Class 11: Transmission Gates, Latches

Transmission Gate 2-to-1 MUX (Martin, c5.1)
Vslct
0
0
0
0

A
0
0
1
1

B
0
1
0
1

Q1(n)
off
off
off
off

Q2(n)
on
on
on
on

C
B
B
B
B

1
1
1
1

0
0
1
1

0
1
0
1

on
on
on
on

off
off
off
off

A
A
A
A

This same design will be revisited shortly for an 8-to-1 MUX

Joseph A. Elias, PhD

Class 11: Transmission Gates, Latches

Transmission Gate XOR (Martin, c5.1)
XOR similar to 2-to-1 MUX
NMOS version:

B
0
0

A
0
1

Q1(n)
off
off

Q2(n)
on
on

C
0 (A)
1 (A)

1
1

0
1

on
on

off
off

1 (A)
0 (A)

CMOS version:

Q2

XOR

NMOS
X-Gate
6

Joseph A. Elias, PhD

pseudo-NMOS
traditional
7

CMOS
X-Gate
8

CMOS
traditional
10

Class 11: Transmission Gates, Latches

Transmission Gate 8-to-1 MUX (Martin, c5.1)
0/1

0/1

0/1

0/1

0/1

0/1

1/0
1/0

0/1
1/0
0/1

0/1

1/0

1/0
1/0

0/1

A2
0
0
0
0

A1
0
0
1
1

A0
0
1
0
1

Y
D0
D4
D2
D6

1
1
1
1
(E / O)

0
0
1
1
(T / B)

0
1
0
1
(D0-D3),
(D4-D7)

D1
D5
D3
D7

1/0

Typically, one would not use more than 8-to-1 MUX. Why?

Joseph A. Elias, PhD

Class 11: Transmission Gates, Latches

Transmission Gate Clocked Latch (Martin, c5.1)
1/0
on/off

off/on
0/1

When CLK is high:

When CLK is low:

Vin

Vin

Vin

Vin

Vin
data is latched to Vin at time
of clock transition

Vin
track mode, latch is loaded
Joseph A. Elias, PhD

Class 11: Transmission Gates, Latches

Voltage Drop of n-CH X-Gates (Martin, c5.1)
Pseudo-NMOS X-Gate
delay line cell

Desired operation:
Start with clk = 1, VG2 = Vin
Transition, clk 1->0, Q1 on->off, Cp keeps voltage
AKA source follower or common drain buffer
Cp is due to what?
Vout = Vin
Problems with circuit:
Start with Vin=0, and clk 0->1
VG2 = Vin = 0V, so Q1 S/D are at ground (Q1 is in what region?)
If Vin -> VDD, while clk = 1, initially LHS of Q1 is drain
RHS is the source, and Vgs=VDD, and Vgd=0
(Q1 is in what region?)
VG2 charges up to VDD-Vtn
Veff for Q1 will become zero (Vgs-Vtn=0)
Q1 shuts off when Vgs=Vtn, or when VG2 = VDD-Vtn
Thus VG2 never gets to VDD, and body effect determines
how far from VDD the node ends up
As body effect goes up, Vtn goes up, VG2 goes down
So what is the problem?
Joseph A. Elias, PhD

Class 11: Transmission Gates, Latches

Voltage Drop of n-CH X-Gates (Martin, c5.1)
Through how many series transistors
does the data pass?
Equivalency says that two series
transistors with W/L is the same
as one transistor with W/2L
Voltage at gate of Q3 is the same,
it just takes longer to rise

=>

Joseph A. Elias, PhD

Class 11: Transmission Gates, Latches

n-CH vs. CMOS X-Gates (Martin, c5.1)

Area may be smaller if NMOS used vs. CMOS

CMOS X-Gates transfer 1 and 0 efficiently. Why?
CMOS X-Gates after faster in 0->1 transition. Why?
N-CH voltage drop a major disadvantage, but can be eliminated
Speed:
When junction capacitance dominates, which should be used?
When load capacitance dominates, which should be used?
Power:
Which is more sensitive to Vt value?
Joseph A. Elias, PhD

Class 11: Transmission Gates, Latches

Full-Swing n-CH X-Gates (Martin, c5.1)
on->off

Applicable when an inverter follows

a pass transistor

on/off

0->1
1->0
0/1

1/0

1->0

Q4 must have W/L small compared to

Q1 for 1->0 at Q2 gate. Why?
p-ch load (Q3) will be completely turned
off with the addition of Q4. If not, what
would occur?

Joseph A. Elias, PhD

10

Class 11: Transmission Gates, Latches

Leakage Currents (Martin, c5.1)
What happens to voltages
when clk is high and Vin=1?
Cp obtains what value?
What happens to Cp if clk remains low
How does this vary with temperature?
What else would cause this to vary?

Joseph A. Elias, PhD

11

Class 11: Transmission Gates, Latches

Static CMOS Digital Latches (Martin, c7.1)
Example of a two cross coupled inverters, having positive feedback:

Latch realized below using what type of logic?

Joseph A. Elias, PhD

12

Class 11: Transmission Gates, Latches

Static CMOS Digital Latches (Martin, c7.1)

What has changed from

previous slide for latch?
When CLK is high, D is passed to V1,
but why is it not inverted by Q5/Q6?
Good: hysteresis is added, noise immunity
for slow-moving signals, less area than
latch of previous foil
Bad: Only inverter a is a driver. Why?

Joseph A. Elias, PhD

13

Class 11: Transmission Gates, Latches

Static CMOS Digital Latches (Martin, c7.1)

Q1 is used as a pass transistor,

so why is Q2 in the circuit?
Q2 ratio W/L should be small or large
compared to Q1?
When CLK is low, Q3 is on,
reinforcing a stored 0 at V1.
What reinforces the stored 1 at V1
when CLK is low?

Joseph A. Elias, PhD

14

Class 11: Transmission Gates, Latches

Static CMOS Digital Latches (Martin, c7.1)

Q
1

Cross coupled NOR gates

Q=D when Clk=1
Q preserved when Clk=0

0
0->1
Q

As CLK 0->1, Q->gnd if

Q5/Q7 widths are larger than Q3
Q5 series with Q7 gives what width?
Compare to what width of Q3?
1
When Q is low, Q4 is on, Q2 off, Q is 1
This means one inverter delay

0->1

Joseph A. Elias, PhD

15