ERROR DETECTION & CORRECTION
Parallel Transmission
Asynchronous and Synchronous Transmission
Timing problems require a mechanism to synchronize the transmitter and receiver Two solutions
Asynchronous
Synchronous
Asynchronous
Data transmitted on character at a time
5
to 8 bits
Timing only needs maintaining within each character Resynchronize with each character
Asynchronous Transmission
Asynchronous (diagram)
Asynchronous - Behavior
In a steady stream, interval between characters is uniform (length of stop element) In idle state, receiver looks for transition 1 to 0 Then samples next seven intervals (char length) Then looks for next 1 to 0 for next char Simple Cheap Overhead of 2 or 3 bits per char (~20%) Good for data with large gaps (keyboard)
Synchronous - Bit Level
Block of data transmitted without start or stop bits Clocks must be synchronized Can use separate clock line
Good
over short distances Subject to impairments
Embed clock signal in data
Manchester
encoding Carrier frequency (analog)
Synchronous Transmission
Synchronous - Block Level
Need to indicate start and end of block Use preamble and postamble
e.g.
series of SYN (hex 16) characters e.g. block of 11111111 patterns ending in 11111110
More efficient (lower overhead) than async
Synchronous (diagram)
Single-bit error
Multiple-bit error
Burst error
Types of Error
An error occurs when a bit is altered between transmission and reception Single bit errors
One bit altered Adjacent bits not affected White noise Length B Contiguous sequence of B bits in which first last and any number of intermediate bits in error Impulse noise Fading in wireless Effect greater at higher data rates
Burst errors
Error Detection Process
Error Detection
Additional bits added by transmitter for error detection code Parity
Value
of parity bit is such that character has even (even parity) or odd (odd parity) number of ones Even number of bit errors goes undetected
Cyclic Redundancy Check (CRC)
21
one of most common and powerful checks for a block of k bits, transmitter generates an n-bit frame by adding an (n-k)-bit frame check sequence (FCS) Transmits n bits which is exactly divisible by some predetermined number receiver divides frame by that number
if
no remainder, assume no error
CRC
Binary Division
Example
Given
Message
D = 1010001101 (10 bits) Pattern P = 110101 (6 bits) FCS (Frame check sequence) R = To be calculated (5 bits)
Values of CRC are normally expressed as polynomials with a dummy variable X Thus, for D = 110011
D(X)
= X5+X4+X+1
And P = 11001 P(X) = X4+X3+1
Calculate
D(X)= X7+X5+X4+X2+X1+X0 P(X) = X5+X4+X1+X0 R(X) = ?
Four versions of P(X) are widely used
CRC-12 = X12+X11+X3+X2+X+1 CRC-16 = X16+X15+X2+1 CRC-CCITT = X16+X12+X5+1 CRC-32 = X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2 +X+1
Error Correction
Correction of detected errors usually requires data block to be retransmitted Not appropriate for wireless applications
Bit
error rate is high
of retransmissions
Lots
Propagation
Would
delay can be long (satellite) compared with frame transmission time
result in retransmission of frame in error plus many subsequent frames
Need to correct errors on basis of bits received
Error Correction Process Diagram
Error Correction Process
Each k bit block mapped to an n bit block (n>k)
Codeword Forward error correction (FEC) encoder
Codeword sent Received bit string similar to transmitted but may contain errors Received code word passed to FEC decoder
If no errors, original data block output Some error patterns can be detected and corrected Some error patterns can be detected but not corrected Some (rare) error patterns are not detected
Results in incorrect data output from FEC
Working of Error Correction
Add redundancy to transmitted message Can deduce original in face of certain level of error rate E.g. block error correction code
In
general, add (n k ) bits to end of block
Gives
n bit block (codeword) All of original k bits included in codeword
Some
FEC map k bit input onto n bit codeword such that original k bits do not appear.
