This is the first of a multi-part series, to introduce FinFET technology to SemiWiki readers.

These articles will highlight the technology's key characteristics, and describe some of the advantages, disadvantages, and challenges associated with this transition. Topics in this series will include FinFET fabrication, modeling, and the resulting impact upon existing EDA tools and flows. (And, of course, feedback from SemiWiki readers will certainly help influence subsequent topics, as well.) Scaling of planar FET's has continued to provide performance, power, and circuit density improvements, up to the 22/20nm process node. Although active research on FinFET devices has been ongoing for more than a decade, their use by a production fab has only recently gained adoption. The basic cross-section of a single FinFET is shown in Figure 1. The key dimensional parameters are the height and thickness of the fin. As with planar devices, the drawn gate length (not shown) separating the source and drain nodes is a critical design dimension. As will be described in the next installment in this series, the h_fin and t_fin measures are defined by the fabrication process, and are not design parameters.

Figure 1. FinFET cross-section, with gate dielectric on fin sidewalls and top, and bulk silicon substrate The FinFET cross-section depicts the gate spanning both sides and the top of the fin. For simplicity, a single gate dielectric layer is shown, abstracting the complex multi-layer dielectrics used to realize an effective oxide thickness (EOT). Similarly, a simple gate layer is shown, abstracting t he multiple materials comprising the (metal) gate. In the research literature, FinFET's have also been fabricated with a thick dielectric layer on top, limiting the gate's electrostatic control on the fin silicon to just the sidewalls. Some researchers have even fabricated independent gate signals, one for each fin sidewall in this case, one gate is the device input

and the other provides the equivalent of FET back bias control. For the remainder of this series, the discussion will focus on the gate configuration shown, with a thin gate dielectric on three sides. (Intel denotes this as Tri-Gate in their recent IvyBridge product announcements.) Due to the more complex fabrication steps (and costs) of dual -gate and independentgate devices, the expectation is that these alternatives will not reach high volume production, despite some of their unique electrical characteristics. Another fabrication alternative is to provide an SOI substrate for the fin, rather than the bulk silicon substrate shown in the figure. In this series, the focus will be on bulk FinFET's, although differences between bulk and SOI substrate fabrication will be highlighted in several examples.

Figure 2. Multiple fins in parallel spaced s_fin apart, common gate input Figure 2 illustrates a cross-section of multiple fins connected in parallel, with a continuous gate material spanning the fins. The Source and Drain nodes of the parallel fins are not visible in this cross-section subsequent figures will show the layout and cross-section view of parallel S/D connections. The use of parallel fins to provide higher drive current introduces a third parameter, the local fin spacing (s_fin). Simplistically, the effective device width of a single fin is: (2*h_fin + t_fin), the total measure of the gate's electrostatic control over the silicon channel. The goal of the fabrication process would be to enable a small fin spacing, so that the FinFET exceeds the device width that a planar FET process would otherwise provide: s_fin < (2*h_fin + t_fin)

Subsequent discussions in this series will review some of the unique characteristics of FinFET's, which result in behavior that differs from the simple (2*h + t) channel surface current width multiplier. The ideal topology of a tall, narrow fin for optimum circuit density is mitigated by the difficulties and variations associated with fabricating a high aspect ratio fin. In practice, an aspect ratio of (h_fin/t_fin ~2:1) is more realistic. One immediate consequence of FinFET circuit design is that the increments of device width are limited to (2h + t), by adding another fin in parallel. Actually, due to the unique means by which fins are patterned, a common device width increment will be (2*(2h+t)), as will be discussed in the next installment in this series. The quantization of device width in FinFET circuit design is definitely different than the continuous values available with planar technology. However, most logic cells already use limited device widths anyway, and custom circuit optimization algorithms typically support snapping to a fixed set of available width values. SRAM arrays and analog circuits are the most impacted by the quantized widths of FinFET's especially SRAM bit cells, where high layout density and robust readability/writeability criteria both need to be satisfied. The underlying bulk silicon substrate from which the fin is fabricated is typically undoped (i.e., a very low impurity concentration per cm**3). The switching input threshold voltage of the FinFET device (Vt) is set by the workfunction potential differences between the gate, dielectric, and (undoped) silicon materials. Although the silicon fin impurity concentration is effectively undoped, the process needs to introduce impurities under the fin as a channel stop, to block punchthrough current between source and drain nodes from carriers not controlled electrostatically by the gate input. The optimum means of introducing the punchthrough-stop impurity region below the fin, without substantially perturbing the (undoped) concentration in the fin volume itself, is an active area of process development. Modern chip designs expect to have multiple Vt device offerings available e.g., a standard Vt, a high Vt, and a low Vt to enable cell-swap optimizations that trade-off performance versus (leakage) power. For example, the delay of an SVT-based logic circuit path could be improved by selectively introducing LVT-based cells, at the expense of higher power. In planar fabrication technologies, multiple Vt device offerings are readily available, using a set of threshold-adjusting impurity implants into masked channel regions. In FinFET technologies, different device thresholds would be provided by an alternative gate metallurgy, with different workfunction potentials. The availability of multiple (nFET and pFET) device thresholds is a good example of the tradeoffs between FinFET's and planar devices. In a planar technology, the cost of additional threshold offerings is relatively low, as the cost of an additional masking step and implant is straightforward. However, the manufacturing variation in planar device Vt's due to channel random dopant fluctuation (RDF) from the implants is high. For FinFET's, the cost of additional gate metallurgy processing for multiple Vt's is higher yet, no impurity introduction into the channel is required, and thus, little RDF-based variation is measured. (Cost, performance, and statistical variation comparisons will come up on several occasions in this series of articles.) The low impurity concentration in the fin also results in less channel scattering when the device is active, improving the carrier mobility and device current.

Conversely, FinFET's introduce other sources of variation, not present with planar devices. The fin edge roughness will result in variation in device Vt and drive current. (Chemical etch steps that are selective to the specific silicon crystal surface orientation of the fin sidewall are used to help reduce roughness.) The characteristics of both planar and FinFET devices depend upon Gate Edge Roughness, as well. The fabrication of the gate traversing the topology over and between fins will increase the GER variation for FinFET devices, as shown in Figure 3.

Figure 3. SEM cross-section of multiple fins. Gate edge roughness over the fin is highlighted in the expanded inset picture. From Baravelli, et al, Impact of Line Edge Roughness and Random Dopant Fluctuation on FinFET Matching Performance, IEEE Transactions on Nanotechnology, v.7(3), May 2008. The major process steps in fabricating silicon fins are shown in Figures 1 through 3. The step that defines the fin thickness uses Sidewall Image Transfer (SIT). Low-pressure chemical vapor (isotropic) deposition provides a unique dielectric profile on the sidewalls of the sacrificial patterned line. A subsequent (anisotropic) etch of the dielectric retains the sidewall material (Figure 1). Reactive ion etching of the sacrificial line and the exposed substrate results in silicon pedestals (Figure 2). Deposition of a dielectric to completely fill the volume between pedestals is followed by a controlled etch-back to expose the fins (Figure 3).

Figure 1. Cross-section of sidewalls on sacrificial lines after CVD etch.

Figure 2. Cross-section of silicon pedestals after RIE etch, using Sidewall Image Transfer.

Figure 3. Cross-section of silicon fins after oxide deposition and etch-back, and gate deposition. Low-pressure dielectric deposition to create sidewalls on a polysilicon line is a well-known technique it is commonly used to separate (deep) source/drain implant areas from the planar FET transistor channel. FinFET fabrication extends this technique to pattern definition for silicon fin etching. There is no photolithography step associated with SIT, just the patterning of the sacrificial lines. As a result, the fin thickness can be smaller than the photolithographic minimum dimensions. The fin thickness is defined by well-controlled dielectric deposition and etching steps rather than photoresist patterning, reducing the manufacturing variation. However, there is variation in fin height, resulting from (local) variations in the etch-back rate of dielectric removal. (For FinFET's on an SOI substrate, the fin height is defined by the silicon layer thickness, with a 'natural' silicon etch-stop at the insulator interface in contrast to the timed-etch fin height for bulk substrate pedestals.) There are several characteristics to note about SIT technology. Nominally, fins come in pairs from the two sidewalls of the sacrificial line. Adding fins in parallel to increase drive current typically involves adding a pair of fins: delta_w = (2*(2*h_fin + t_fin)). To cut fins, a masked silicon etching step is required. There are two considerations for cutting fins. The

first involves breaking long fins into individual pairs. The other is to create an isolated fin, by removing its SIT-generated neighbor. Critical circuits that require high density and/or different device sizing ratios may justify the need for isolated fin patterning e.g., SRAM bit cells. Compared to cutting, isolated fin patterning may involve different design rules and separate (critical) lithography steps, and thus additional costs. Additional process steps are required to introduce impurities of the appropriate type below the fin to provide a punchthrough stop (PTS), ensuring there is no direct current path between drain and source that is not electrostatically controlled by the gate input. The dielectric between pedestals that remains after etch-back serves as the field oxide, as denoted in Figure 3. The gate material traversing between parallel fins is well-separated from the substrate, minimizing the Cgx parasitic capacitance. The uniformity and control of the final fin dimensions are important process characteristics, for both the fin thickness and fin corner profiles. (The profile of the pedestal below the fin is less critical, and may be quite tapered, as shown in Figure 3.) Tolerances in the fin thickness arise from variations in the vertical, anisotropic SIT silicon etch. The fin thickness at the bottom is also dependent upon the uniformity of the etch-back the goal is to minimize any dielectric foot remaining at the bottom of th e fin. As will be discussed in the next series installment, variations in t_fin have significant impact upon the transistor model. The top corner profiles also have an impact upon the transistor behavior, as the electric fields from the gate to the silicon fin are concentrated in this region, originating from both the sidewall and top gate materials. Gate patterning follows conventional photolithographic steps, although the recent introduction of metal gate materials has certainly added to the complexity, especially as the gate must now traverse conformally over parallel fins. As with a planar FET technology, the gate length is the 'critical dimension' that is typically quoted as the basis for the process node e.g., 20nm. In contrast to planar FET technologies, providing multiple FinFET threshold voltage (Vt) offerings requires significant additional process engineering. The threshold of any FET is a function of the workfunction potential differences between the gate, dielectric, and silicon substrate interfaces. In planar FET's, multiple Vt offerings are readily provided by shallow (masked) impurity implants into the substrate prior to gate deposition, adjusting the workfunction potential between dielectric and channel. However, the variation in the (very small) dosage of impurities introduced in the planar channel results in significant Vt variation, due to 'random dopant fluctuation' (RDF). With FinFET's, there is ongoing process development to provide different metal gate compositions (and thus, metal-to-dielectric workfunctions) as the preferred method for Vt adjust. The advantage of using multiple gate metals will be to reduce the RDF source of Vt variation substantially, as compared to implanting a (very, very small) impurity dosage into the fin volume. The disadvantage is the additional process complexity and cost of providing multiple metal gate compositions. Another key FinFET process technology development is the fabrication of the source/drain regions. As was mentioned in the first series installment, the silicon fin is effectively undoped. Although

advantageous for the device characteristics, the undoped fin results in high series resistance outside the transistor channel, which would otherwise negate the drive current benefits of the FinFET topology. To reduce the Rs and Rd parasitics, a spacer oxide is deposited on the FinFET gate sidewalls, in the same manner as sidewalls were patterned earlier for SIT fin etching. To increase the volume of the source/drain, a 'silicon epitaxy growth' (SEG) step is used. The exposed S/D regions of the original fin serve as the seed for epitaxial growth, separated from the FinFET gate by the sidewall spacer. Figure 4 shows the source/drain cross-section after the SEG step.

Figure 4. Cross section of source/drain region, after epitaxial growth. Original fin is in blue -- note the faceted growth volume. The current density in the S/D past the device channel to the silicide top is very non-uniform. From Kawasaki, et al, IEDM 2009, p. 289-292. The incorporation of impurities of the appropriate type (for nFET or pFET) during epitaxial growth reduces the S/D resistivity to a more tolerable level. The resistivity is further reduced by silicidation of the top of the S/D region. In the case of pFET's, the incorporation of a small % of Ge during this epitaxy step transfers silicon crystal stress to the channel, increasing hole carrier mobility significantly. Raised S/D epitaxy has been used to reduce Rs/Rd for planar FET's, as well. However, there are a couple of interesting characteristics to FinFET S/D process engineering, due to the nature of the exposed fin S/D nodes, compared to a planar surface. The epitaxial growth from the exposed crystalline surface of the silicon fin results in a faceted volume for the S/D regions. Depending upon the fin spacing and the amount of epitaxial growth, the S/D regions of parallel fins could remain isolated, or could potentially merge into a continuous volume. The topography of the top surface for subsequent metallization coverage is very uneven. The current

distribution in the S/D nodes outside the channel (and thus, the effective Rs and Rd) is quite complex. FinFET's could be fabricated with either a HKMG 'gate-first' or a 'gate-last' process, although gate-last is likely to be the prevalent option. In a gate-last sequence, a dummy polysilicon gate is initially patterned and used for S/D formation, then the gate is removed and the replacement metal gate composition is patterned. FinFET's also require a unique process step after gate patterning and S/D node formation, to suitably fill the three-dimensional grid of parallel fins and series gates with a robust (low K) dielectric material. Contacts to the S/D (and gate) will leverage the local interconnect metallization layer that has recently been added for planar 20nm technologies.
The introduction of FinFET Technology has opened new chapters in Nano-technology. Simulations show that FinFET structure should be scalable down to 10 nm. Formation of ultra thin fin enables suppressed short channel effects. It is an attractive successor to the single gate MOSFET by virtue of its superior electrostatic properties and comparative ease of manufacturability. Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.

Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high-speed devices and in very large-scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of

fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite sub threshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the offstate leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin. Alternative device structures based on silicon-on-insulator (SOI) technology have emerged as an effective means of extending MOS scaling beyond bulk limits for mainstream high-performance or lowpower applications .Partially depleted (PD) SOIwas the first SOI technology introduced for high-performance microprocessor applications. The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device structures promise to be the potential "future" technology/device choices. In these device structures, the short-channel effect is controlled by geometry, and the thin Si film limits the offstate leakage.
INTRODUCTION

The introduction of FinFET Technology has opened new chapters in Nano-technology. Simulations show that FinFET structure should be scalable down to 10 nm. Formation of ultra thin fin enables suppressed short channel effects. It is an attractive successor to the single gate MOSFET by virtue of its superior electrostatic properties and comparative ease of manufacturability. Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure.The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.

ARCHITECTURE

This method provides a SiGe-based bulk integration scheme for generating FinFET devices on a bulk Si substrate in which a simple etch, mask, ion implant set of sequences have been added to accomplish good junction isolation while maintaining the low capacitance benefits of FinFETs. Specifically, the method of the present invention includes the steps of: providing a structure including a bottom Si layer and a patterned stack comprising a SiGe layer and a top Si layer on said bottom Si layer; forming a well region and isolation regions via implantation within said bottom Si layer; forming an undercut region beneath said top Si layer by etching back said SiGe layer; and filling said undercut with a dielectric to provide device isolation, wherein said dielectric has an outer vertical edge that is aligned to an outer vertical edge of said top Si layer.

ADVANTAGES Due to their high immunity to short channel effects, importance of MOSFET with multiple gates (MUGFET) or FinFETs are increased by technologists for sub-100nm. Especially for the digital applications, numerous FinFET realizations have reported with effective and improved feasibility, economy and performance with respect to up to date CMOS bulk technologies. Since, the FinFETs have better electrostatic channel control characteristic with improved turn off, they are considered as promising candidate for the futures fulfilling CMOS device demands.

APPLICATIONS FinFETs have a wide variety of applications. Some of these are pointed here. Transconductance Amplifier Using Finfet Technology Due to their high immunity to short channel effects, importance of MOSFET with multiple gates (MUGFET) or FinFETs are increased by technologists for sub-100nm . Especially for the digital applications, numerous FinFET realizations have reported with effective and improved feasibility, economy and performance with respect to up to date CMOS bulk technologies . Since, the FinFETs have better electrostatic channel control characteristic with improved turn off, they are considered as promising candidate for the futures fulfilling CMOS device demands. In addition to excellent channel control, the FinFET transistors also offer approximately twice the on-current because of the two channels, even without channel doping. This is beneficial for the carrier mobility and results in a low gate leakage at the same time