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Processor Design Single Cycle Processor: Hung-Wei Tseng

The document discusses the design of a single-cycle MIPS processor. It describes the basic steps of instruction execution in a single-cycle processor as instruction fetch, decode, execute, and write back. It then discusses in detail how the datapath elements like instruction memory, register file, ALU, and program counter are accessed for different MIPS instruction types like R-type, load, store, and branch instructions in the single cycle. It also covers some questions about the number of datapath elements needed and order of accessing them for different instructions. Finally, it discusses performance aspects of a single-cycle processor.

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64 views20 pages

Processor Design Single Cycle Processor: Hung-Wei Tseng

The document discusses the design of a single-cycle MIPS processor. It describes the basic steps of instruction execution in a single-cycle processor as instruction fetch, decode, execute, and write back. It then discusses in detail how the datapath elements like instruction memory, register file, ALU, and program counter are accessed for different MIPS instruction types like R-type, load, store, and branch instructions in the single cycle. It also covers some questions about the number of datapath elements needed and order of accessing them for different instructions. Finally, it discusses performance aspects of a single-cycle processor.

Uploaded by

wraith324
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Processor Design

Single Cycle Processor


Hung-Wei Tseng
Recap: the stored-program computer

Store instructions in
memory

The program counter


(PC) controls the
execution
2
Processor
PC
120007a30: 0f00bb27 ldah gp,15(t12)
120007a34: 509cbd23 lda gp,-25520(gp)
120007a38: 00005d24 ldah t1,0(gp)
120007a3c: 0000bd24 ldah t4,0(gp)
120007a40: 2ca422a0 ldl t0,-23508(t1)
120007a44: 130020e4 beq t0,120007a94
120007a48: 00003d24 ldah t0,0(gp)
120007a4c: 2ca4e2b3 stl zero,-23508(t1)
i
n
s
t
r
u
c
t
i
o
n

m
e
m
o
r
y
800bf9000: 00c2e800 12773376
800bf9004: 00000008 8
800bf9008: 00c2f000 12775424
800bf900c: 00000008 8
800bf9010: 00c2f800 12777472
800bf9014: 00000008 8
800bf9018: 00c30000 12779520
800bf901c: 00000008 8
d
a
t
a

m
e
m
o
r
y
Recap: MIPS ISA

R-type: add, sub, and etc...

I-type: addi, lw, sw, beq, and etc...

J-type: j, jal, and etc...


3
opcode rs rt rd
shift
amount
funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
opcode target
6 bits 26 bits
Outline

Implementing a MIPS processor

Single-cycle processor

Pipelined processor
4
Designing a simple MIPS processor

Support MIPS ISA in hardware

Design the datapath: add and connect all the required elements
in the right order

Design the control path: control each datapath element to


function correctly.

Starts from designing a single cycle processor

Each instruction takes exactly one cycle to execute


5
Basic steps of execution

Instruction fetch: fetch an


instruction from memory

Decode:

Whats the instruction?

Where are the operands?

Execute

Memory access

Where is my data? (The data


memory address)

Write back

Where to put the result

Determine the next PC


6
Processor
PC
120007a30: 0f00bb27 ldah gp,15(t12)
120007a34: 509cbd23 lda gp,-25520(gp)
120007a38: 00005d24 ldah t1,0(gp)
120007a3c: 0000bd24 ldah t4,0(gp)
120007a40: 2ca422a0 ldl t0,-23508(t1)
120007a44: 130020e4 beq t0,120007a94
120007a48: 00003d24 ldah t0,0(gp)
120007a4c: 2ca4e2b3 stl zero,-23508(t1)
i
n
s
t
r
u
c
t
i
o
n

m
e
m
o
r
y
d
a
t
a

m
e
m
o
r
y
800bf9000: 00c2e800 12773376
800bf9004: 00000008 8
800bf9008: 00c2f000 12775424
800bf900c: 00000008 8
800bf9010: 00c2f800 12777472
800bf9014: 00000008 8
800bf9018: 00c30000 12779520
800bf901c: 00000008 8
R0
R1
R2
R31
.
.
.
.
.
.
.
.
registers
ALU
Recap: MIPS ISA

R-type: add, sub, and etc...

I-type: addi, lw, sw, beq, and etc...

J-type: j, jal, and etc...


7
opcode rs rt rd
shift
amount
funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
opcode target
6 bits 26 bits
Implementing an R-type instruction

How many of the following datapath elements is


necessary for an R-type instruction?
I. Instruction Memory
II. Data memory
III. Register le
IV. Program counter
V. ALU
A. 1
B. 2
C. 3
D. 4
E. 5
8
opcode rs rt rd shift amt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
instruction = MEM[PC]
REG[rd] = REG[rs] op REG[rt]
PC = PC + 4
Implementing an R-type instruction

Whats right order of accessing the datapath elements


for an R-type instruction?
I. Instruction Memory
II. Data memory
III. Register le
IV. Program counter
V. ALU
A. I, III, V, IV
B. IV, I, III, V
C. I, V, III, IV
D. IV, V, I, III
E. none of the above
9
Implementing an R-type instruction
10
opcode rs rt rd shift amt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
instruction = MEM[PC]
REG[rd] = REG[rs] op REG[rt]
PC = PC + 4
!"#$
%$$&"''
!"#$%&'()"
*+,)%-
.
/
012
(&)*" ,#*#
3
044
!"#$
,#*# -
!"#$
,#*# .
!"#$ !"/ -
!"#$ !"/ .
(&)*" !"/
5+67#$+%
879+
inst[25:21]
inst[20:16]
inst[15:11]
inst[31:0]
ALUop
ALU
control
ALUop
Clock
Tell the ALU what
ALU function to
perform
Tell the Processor
when to start an
instruction
Implementing a load instruction

How many of the following datapath elements is


necessary for a load instruction?
I. Instruction Memory
II. Data memory
III. Register le
IV. Program counter
V. ALU
A. 1
B. 2
C. 3
D. 4
E. 5
11
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
instruction = MEM[PC]
REG[rt] = MEM[signext(immediate) + REG[rs]]
PC = PC + 4
Implementing a load instruction

Whats right order of accessing the datapath elements


for a load instruction?
I. Instruction Memory
II. Data memory
III. Register le
IV. Program counter
V. ALU
A. IV, I, III, V, II
B. IV, I, III, II, V
C. IV, I, V, II, III
D. IV, I, II, V, III
E. none of the above
12
Implementing a load instruction
13
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
instruction = MEM[PC]
REG[rt] = MEM[signext(immediate) + REG[rs]]
PC = PC + 4
!"#$
%$$&"''
!"#$%&'()"
*+,)%-
.
/
012
(&)*" ,#*#
3
044
!"#$
,#*# -
!"#$
,#*# .
!"#$ !"/ -
!"#$ !"/ .
(&)*" !"/
5+67#$+%
879+
inst[25:21]
inst[20:16]
inst[15:11]
inst[31:0]
m
u
x
0
1
m
u
x
0
1 sign-
extend
0. -1
:;$;
*+,)%-
%$$&"''
!"#$
,#*#
m
u
x
1
0
ALUop
ALUSrc
MemtoReg
MemRead
RegDst
inst[31:26]
control
Set different control
signals for different types
of instructions
Set to 0 if its a load
Set to 1 if its a load
Set to 1 if its a load
Implementing a store instruction

How many of the following datapath elements is


necessary for a store instruction?
I. Instruction Memory
II. Data memory
III. Register le
IV. Program counter
V. ALU
A. 1
B. 2
C. 3
D. 4
E. 5
14
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
instruction = MEM[PC]
MEM[signext(immediate) + REG[rs]] = REG[rt]
PC = PC + 4
Implementing a store instruction

Whats right order of accessing the datapath elements


for a store instruction?
I. Instruction Memory
II. Data memory
III. Register le
IV. Program counter
V. ALU
A. IV, I, III, V, II
B. IV, I, III, II, V
C. IV, I, V, II, III
D. IV, I, II, V, III
E. none of the above
15
Implementing a store instruction
16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
instruction = MEM[PC]
MEM[signext(immediate) + REG[rs]] = REG[rt]
PC = PC + 4
!"#$
%$$&"''
!"#$%&'()"
*+,)%-
.
/
012
(&)*" ,#*#
3
044
!"#$
,#*# -
!"#$
,#*# .
!"#$ !"/ -
!"#$ !"/ .
(&)*" !"/
5+67#$+%
879+
inst[25:21]
inst[20:16]
inst[15:11]
inst[31:0]
m
u
x
0
1
m
u
x
0
1 sign-
extend
0. -1
:;$;
*+,)%-
%$$&"''
!"#$
,#*#
m
u
x
1
0
(&)*" ,#*#
ALUSrc
MemtoReg
MemRead
RegDst
RegWrite MemWrite
ALUop
inst[31:26]
control
Set to 0 if
its a store
Set to 1 if its a
store
Set to 0 if
its a store
Implementing a branch instruction

How many of the following datapath elements is


necessary for a branch instruction?
I. Instruction Memory
II. Data memory
III. Register le
IV. Program counter
V. ALU
A. 1
B. 2
C. 3
D. 4
E. 5
17
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
instruction = MEM[PC]
PC = (REG[rs] == REG[rt]) ? PC + 4 + SignExtImmediate *4 : PC + 4
Implementing a branch instruction
18
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
instruction = MEM[PC]
PC = (REG[rs] == REG[rt]) ? PC + 4 + SignExtImmediate *4 : PC + 4
!"#$
%$$&"''
!"#$%&'()"
*+,)%-
.
/
012
(&)*" ,#*#
3
044
!"#$
,#*# -
!"#$
,#*# .
!"#$ !"/ -
!"#$ !"/ .
(&)*" !"/
5+67#$+%
879+
inst[25:21]
inst[20:16]
inst[15:11]
inst[31:0]
m
u
x
0
1
m
u
x
0
1 sign-
extend
0. -1
:;$;
*+,)%-
%$$&"''
!"#$
,#*#
m
u
x
1
0
(&)*" ,#*#
m
u
x
1
0
044
<=7>
9+> @
ALUSrc
MemtoReg
MemRead
RegDst
RegWrite MemWrite
PCSrc
2"&3
PCSrc = Branch & Zero
ALUop
inst[31:26]
control
Calculate the
target address
Performance of a single-cycle
processor

How many of the following statements about a single-


cycle processor is correct?

The CPI of a single-cycle processor is always 1

If the single-cycle implements lw, sw, beq, and add instructions,


the sw instruction determines the cycle time

Hardware elements are mostly idle during a cycle

We can always reduce the cycle time of a single-cycle


processor by supporting fewer instructions
19
A. 0
B. 1
C. 2
D. 3
E. 4
Q & A
20

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