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MIPS Registers and Instruction Formats

The document describes the MIPS register set and instruction formats. It provides details on the 32 registers - their names, purposes and encoding. It describes the three main instruction formats - R, I and J types. The R-type includes addition and uses five registers. The I-type includes load and store instructions and uses a register and memory address. Pseudo-instructions make assembly code simpler by translating to multiple machine instructions. Logical operations like shift and AND manipulate data in registers.

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174 views9 pages

MIPS Registers and Instruction Formats

The document describes the MIPS register set and instruction formats. It provides details on the 32 registers - their names, purposes and encoding. It describes the three main instruction formats - R, I and J types. The R-type includes addition and uses five registers. The I-type includes load and store instructions and uses a register and memory address. Pseudo-instructions make assembly code simpler by translating to multiple machine instructions. Logical operations like shift and AND manipulate data in registers.

Uploaded by

doomachaley
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

MIPS registers

register

assembly name Comment

r0

$zero

Always 0

r1

$at

Reserved for assembler

r2-r3

$v0-$v1

Stores results

r4-r7

$a0-$a3

Stores arguments

r8-r15

$t0-$t7

Temporaries, not saved

r16-r23

$s0-$s7

Contents saved for later use

r24-r25

$t8-$t9

More temporaries, not saved

r26-r27

$k0-$k1

Reserved by operating system

r28

$gp

Global pointer

r29

$sp

Stack pointer

r30

$fp

Frame pointer

r31

$ra

Return address

MIPS insruction formats


Instruction add belongs to the R-type format.

opcode

rs

rt

rd

src

src

add $s1, $s2, $t0

shift amt function


5

dst

will be coded as

18

17

32
5

The function field is an extension of the opcode, and


they together determine the operation.

Note that sub has a similar format.

Instruction lw (load word) belongs to I-type format.

opcode

rs

rt

16

base

dst

offset

lw $t0, 32($s3)

address

will be coded as

35

19

32
16

Both lw and sw (store word) belong to I-format.

MIPS has (fortunately) only three different instruction


formats. The operation codes determine the format. This
is how the control unit interprets the instructions.

What is an Assembler?
A simple piece
of software

Assembly
Language

Assembler

Machine
Language

lw t0, 32($s3)

Binary code:

add $s1, $s2, $t0

Consists of 0s and 1s only

If you know the instruction formats, then you can


translate it. The machine language consists of 0s
and 1s

Pseudo-instructions
(Makes your life a bit simpler)
These are simple assembly language instructions that do
not have a direct machine language equivalent. During
assembly, the assembler translates each pseudoinstruction into one or more machine language
instructions.

Example
move $t0, $t1

# $t0 $t1

The assembler will translate it to


add $t0, $zer0, $t1
We will see more of these soon.

Think about these


Q1. How will you load a constant into a memory
location (i.e. consider implementing x :=3)?
(Need some immediate mode instructions, like li
which is a pseudo-instruction)
Q2. How will you implement x:= x+1 in assembly
language?
What do you think?
Q3. Why is the load (and store too) instruction so
crooked?
Used for its flexibility, let us discuss it.
Q4. How will you load a constant (say 5) into a
register?
(Need the immediate mode instructions, like addi)

Loading a 32-bit constant into a register


The pseudo-instruction load immediate

li $s0, 0x 003A0012
hexadecimal

means load the 32-bit constant into register $s0.


Internally it is translated into

lui $s0, 42

# load upper-half immediate

ori $s0, $s0, 18

# (one can also use andi)

Logical Operations
Shift left (logical)

sll

Shift right (logical)

srl

Bit-by-bit AND

and, andi (and immediate)

opcode

rs

rt

rd

src

src

shift amt function


5

dst

sll $t2, $s0, 4 means $t2 = $s0 << 4 bit position


(s0 = $16, t2 = $10)
0
6

16

10

4
5

0
6

s0 = 0000 0000 0000 0000 0000 0000 0000 1001


t2 = 0000 0000 0000 0000 0000 0000 1001 0000

Why are these instructions useful?

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