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Rahul MSEE

This document is a resume for Rahul Sharma, who is seeking a full-time job in the semiconductor industry utilizing his knowledge of semiconductor devices, low power design techniques, and computer architecture. He has a Master's degree in VLSI design from Illinois Institute of Technology and relevant work experience including 6 months of research in low power design and 5 months as a research assistant developing 32-bit LDPC codes. His technical skills include Verilog, VHDL, and CAD tools. He has completed academic projects in low power SRAM design, 32-bit MIPS pipeline design, CAD tool development, and 4-bit domino adder design.

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Rahul Sharma
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95 views2 pages

Rahul MSEE

This document is a resume for Rahul Sharma, who is seeking a full-time job in the semiconductor industry utilizing his knowledge of semiconductor devices, low power design techniques, and computer architecture. He has a Master's degree in VLSI design from Illinois Institute of Technology and relevant work experience including 6 months of research in low power design and 5 months as a research assistant developing 32-bit LDPC codes. His technical skills include Verilog, VHDL, and CAD tools. He has completed academic projects in low power SRAM design, 32-bit MIPS pipeline design, CAD tool development, and 4-bit domino adder design.

Uploaded by

Rahul Sharma
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd

Rahul Sharma (91)9958381152

E-25, Nawada Housing Complex, [Link]@[Link]


Kakrola Chowk, Uttam Nagar
New Delhi 110059.

Dedicated VLSI Engineer with extensive research background in semiconductor industry.

OBJECTIVE

Seeking full time job in Semiconductor Industry where I can use my knowledge of Semiconductor
Devices, Low Power Design Techniques, and Computer Architecture.

CAREER SUMMARY
 Master of Science graduate in VLSI
 6 months research work in low power design
 5 months as research assistant for developing 32 bit LDPC codes
 Hands on experience on many Design and Verification tools

EDUCATION

 M.S.E.E in VLSI Design, ILLINOIS INSTITUTE of TECHNOLOGY, Chicago, IL Aug 2007- Dec 2009
 B.E in Electronics and Communication from M.D.U. Rohtak, Haryana, India Aug 2001- May 2005

RELEVANT COURSES

 Advanced Computer Architecture


 Advanced VLSI systems and design
 Independent Project on low power design
 CAD techniques VLSI design

TECHNICAL SKILLS

 Languages : C, TCL/TK, VERILOG, VHDL, PERL ( adequate )


 Tools : Cadence Virtuoso IC 6.1.0, Analog Design Environment, HSPICE, MAGIC, ModelSim,
NANOSIM, XILINX ISE

ACADEMIC PROJECTS

Power analysis and reduction in 64X512 SRAM array. Jan 2009 – May 2009

 Selected dual threshold voltage and dual gate oxide thickness transistors for power reduction
 Designed and deployed different configurations of six-transistor SRAM cells corresponding to
different threshold voltage and oxide thickness assignments for the transistors
 Each SRAM cell was evaluated for delay and power dissipation

PROBLEM/SOLUTION

 Observed from simulation, high threshold voltage and thick gate oxide transistors weren’t able to
turn on despite of full swing. Careful observation showed that the threshold voltage of these
transistors was very high. After reading several articles about 45 nm Technology, an
approximation of threshold voltages have been made and the file, [Link], was
updated accordingly
Design of 32 bit MIPS Pipeline Architecture. Feb 2009 – May 2009

 Implemented forwarding technique to avoid data hazards


 Implemented extra hardware to avoid stalls during store instructions
 Reduced stall for branch hazard by one clock cycle by designing program counter differently

PROBLEM/SOLUTION

 Waveform simulation showed, due to small clock cycle period, the data was not written in register
file in first half cycle and be ready to be read in second half cycle. I designed a new technique by
implementing a pair of MUX at the output of register file so as to read correct data

CAD tool design Sept 2008 – Dec 2008

For hierarchical gate level netlist.

 Designed tool for hierarchical gate-level netlist display for synthesized 4bit, 8bit, and 16bit Ripple
carry adder
 Tool accepted 4bit, 8bit, and 16bit Ripple Carry Adder’s netlist as input
 Based on input, 4bit, 8bit, or 16bit adder netlist, the tool demonstrated hierarchy of gate level
netlist graphically

For static timing analysis for digital circuits.

 Implemented graph based time slack analysis for digital circuits


 Arrival time, required time, and slack were calculated

Four bit domino adder design Mar 2008 – May 2008

 Designed two 4bit domino full adders one with low threshold and other with high threshold voltage
transistors and performance comparison was made based on leakage power and delay
 Keepers were used to avoid charge sharing and transistor sizing was done for proper output

PERSONAL INTEREST

 Photography, Traveling

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