Laboratory Exercise # 1

Introduction to Logic Simulation and Verilog

VLSI Design
Department of Electronics & Communication
Marwadi Education Foundation Group of Institution
Laboratory Exercise 1

1 Introduction
In the previous labs, we tested and debugged our digital designs by bread-boarding the actual circuits using
ICs. For small designs, this method proved to be quite effective, and in the late 1960’s and early 1970’s,
this was standard practice. However, as the gate counts of our circuits increased, this method became far
less attractive. Thankfully, with advances in computer technology, there are alternatives to bread-boarding
circuits. In this day and age, we can effectively simulate the operation of our digital circuits during the
design process without being burdened with the tedium you all have experienced up to this point. In lab this
week, we will demonstrate the concept of digital circuit simulation and, in doing so, introduce Verilog R
HDL, an Institute of Electrical and Electronics Engineers (IEEE) standard Hardware Description Language
(HDL).

2 Background
The following subsections will provide you with some of the background necessary to understand and ap-
preciate the way modern digital design is carried out. For a more in-depth treatment, please consult the
course text book.

2.1 Verilog HDL

Programming languages have proven to be effective for software development. Interestingly, a similar truth
holds for hardware development. Just as programming languages boost developer productivity, Hardware
Description Languages (HDLs) do so through various levels of abstraction, while providing a means to suc-
cinctly describe digital circuits. What differentiates a traditional programming language from a standard
HDL is the manner in which operations described within the language are handled. In a tradition program-
ming language such as C, operations happen sequentially, and conditional statements facilitate changes in
program flow. In contrast, the operations described in an HDL happen concurrently, and signals (often called
nets) allow concurrent operations to interact with one another.
In the 1980’s, two competing HDLs were developed, namely VHDL and Verilog. Today, both languages
co-exist, encouraging tool vendors to support VHDL and Verilog simultaneously within a single design. For
our work in this lab, we will concentrate on Verilog; however, it is important to note that many of the
HDL principals demonstrated here apply to VHDL as well. Verilog offers various levels of abstraction for
describing digital circuits with structural at the bottom and behavioral at the top. Any given design could
have a mixture of these abstraction levels, but in this lab assignment, we will start at the lowest level and
move up. The example shown below uses structural Verilog and the gate-level primitives built into Verilog
to describe the 1-bit wide, 2:1 multiplexer you designed in the previous lab. The corresponding gate-level
schematic in Figure 1 labels the module ports, internal wires, and gate instance names according to the
provided Verilog code.

Figure 1: Gate-level Schematic of a 1-bit wide, 2:1 MUX

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‘ timescale 1 ns/1 ps
‘ default nettype none
/ ∗ This module describes a 1− bit wide multiplexer using structural constructs ∗ /
/∗ and gate – level primitives built into Verilog. ∗ /

Module two_one_mux ( Y , A , B , S ) ;
// define the module name and its interface
/ ∗ declare output and input ports ∗ /

/ ∗ declare internal nets ∗ /

wire notS ; // inverse of S
wire andA ; / / output of and0 gate
wire andB ; / / output of and1 gate

/∗instantiate gate−level modules∗/

not not0 ( notS , S ) ;
and and0 ( andA , notS , A ) ;
and a n d 1 ( andB , S , B ) ;
or or0 ( Y , andA , andB ) ;

endmodule / / d e s i g n a t e end o f modul e

Syntactically, Verilog is very similar to the C programming language. Comments are designated in a
similar fashion (i.e. n\* */= for comments which span multiple lines or \\ for single line comments), and
semicolons end declarations, assignments, and statements. Verilog is case-sensitive and all keywords are
lowercase. The keyword, module, marks the beginning of the Verilog module, while the keyword,
endmodule, marks the end. In the example above, the module name is two one mux, and its ports are Y,
A, B, and S. The port order is not enforced by the language but follows a common convention in which the
output ports are first, followed by the input ports. The keyword, output, is used to declare a net as an output
port, while input declares a net as an input port. Nets can be of type wire or reg. For now, we will only
be concerned with wires. Nets can take on one of four values, namely ‘1’, ‘0’, ‘Z’, and ‘X’ for high, low,
floating, and undefined, respectively. Modules, whether built-in or user-defined, are instantiated as seen in
lines 14 through 19 of the code above. The module name is followed by the instance name. The instance
name must obviously be unique; however, multiple instances of the same module may exist. Notice the
order of ports for the built-in primitives (i.e. not, and, or) follows the convention discussed above such that
the output port is first, followed by the input ports. Since these operations are associative, the order of the
inputs is not important.

2.2 Xilinx ISE

Xilinx R Integrated Software Environment (ISETM ) version 13.4 is the hardware development tool that we
Laboratory Exercise 1

will be using in this laboratory. Xilinx manufacturers a wide variety of reprogrammable logic devices (we
will discuss these further in the next lab) and supplies ISE as a means to develop for these devices. Conse-
quently, ISE is an excellent teaching tool for modern digital design. It supports digital circuit simulation,
which is the focus of this week’s lab assignment, in addition to all of the implementation processes neces-
sary to load a design into an Xilinx part. It comes with an easy-to-use Graphical User Interface (GUI) and
waveform viewer and supports both VHDL and Verilog. Xilinx ISE is part of a larger class of computer-
aided design (CAD) tools used to develop digital circuits. For additional information on Xilinx and ISE
13.4, consult the manufacturer’s website at: www.xilinx.com

2.3 Linux OS
Linux is an open-source Unix-like operating system (OS) commonly used in industry. The open-source
license allows it to be used free of charge, which makes it a big win for the university setting. The Unix
aspect allows Linux to be compatible with many of the CAD tools out on the market today. The Linux
kernel along with the various support packages makeup the specific Linux distribution. The machines in the
VLSI lab have a variant of Ubuntu installed on them because manyof the tool vendors will provide support
for only Linux environment.
The Ubuntu Linux installation has a window manager, which gives you the look and feel similar to that
of MS Windows or MacOS. However, the Linux terminal is available for those acquainted with Unix. As a
result, you will be provided with commands to execute in the terminal throughout the lab session. Please try
to understand what these commands do so that you can execute them in future labs without instruction. The
format of the commands provided is shown below. The command to be executed follows the > symbol.

>command argument0 argument1

Note: Please ensure that you have a Unix account with the ECE department before arriving to your
lab session. It is imperative that you are able to log into the Ubuntu machines.

3 Pre-lab
We will reuse the designs created previous year in Digital Electronics. So you have to come with the
concept of ALU using gates. Concept of digital gates, combinational logic. You have to prepare a short
note on ALU design using combinational logic on paper. Here you have to draw the final design.

4 Lab Procedure
The lab experiments below will guide you through the development of a simple 4-bit ALU in Verilog
using the ISE software suite. Each module that you create will be individually tested using the built-in
digital circuit simulator, ISim, with test bench files that we provide to you.

4.1 Experiment 1
The objective of this lab experiment is to familiarize you with the ISE development environment.
Please take note of what it is you are doing as you will be expected to perform similar exercises on
your own in future experiments.
 Laboratory Exercise 1

1. Launch ISE Project Navigator and create a new design project.

(a) Open a terminal window in the Ubuntu workstation by selecting Applications →
Accessories→ Terminal and type the following command and hit “Enter” to create a work
directory:

> mkdir $HOME/VLSI

(b) Now execute the following command to run ISE:

>/softwares/setup/xilinx/ise-13.4

(c) Once ISE loads, select File → New Project

The New Project Wizard will open as illustrated below. Type a Project Name (ex. lab6) and a
Project Location (ex. /vlsi/lab1 in your home directory). Then chose HDL as the Top-Level
Source Type and click “Next.”

(d) Next, the ‘Project Settings’ window appears (see screenshot below).
Set the following project settings:

Evaluation Development Board: Spartan-3E Starter Board

Simulator: ISim (VHDL/Verilog) Preferred Language: Verilog
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(e) Hit “Next” to continue. A Project Summary window will appear. Examine the summary
and click “Finish” when done.

2. Create a Verilog source file which describes the 2:1 MUX in Figure 1.

(a) From within ISE, select File → New to create a new file.

(b) A dialog box will appear as seen above. Select “Text File” and press “OK.”

(c) Type the Verilog code example found the in the Background section of this manual into the
ISE text editor window.
Note: Do NOT copy and paste text from the PDF into the editor window. Symbols within the
code do not always copy properly and will cause syntax errors when you attempt to build the
project.

(d) Select File → Save and save the file you just created as “two one mux.v” within your lab1
directory.

3. Add the 2:1 MUX source file and test bench to the ISE project.

(a) Right-click on the Xilinx part number (xc3s500e-4fg320) within the Hierarchy window and
select “Add Source...” as shown in below.
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(b) In the file browser, navigate to the source file you just created and hit “Open.”

(c) A window will appear with Association and Library fields. Leave these settings as default
and press “OK” to continue.

(d) Ensure the source file you just added appears under the Xilinx part number in the Hierarchy
window.

(e) Open a new terminal window and copy the appropriate test bench file from the ECEN248
directory into you lab1 directory with the following commands:
>cd $HOME/VLSI/Lab1
>cp HOME/VLSI/Faculty/Lab1/two_one_mux_tb.v
The first command changes the current directory to your lab1 directory, while the second
command copies the 2:1 MUX test bench into the current directory. You could also
perform this operation in a single command by replacing the ‘.’ at the end of the copy
command with the path to your lab1 directory.
Laboratory Exercise 1

(f) Add the “two one mux tb.v” file to your ISE project, leaving the source file properties as
default again.

(g) Change the “View” setting within the Hierarchy window to “Simulation” and ensure the
hierarchy appears as seen in below.

(h) Open the 2:1 MUX test bench file and take a moment to examine the contents. The test
bench utilizes advanced concepts in Verilog that we have not discussed yet, but some
things should look familiar. A test bench file is nothing more than a Verilog module
which instantiates the Unit Under Test (UUT) and stimulates the inputs for testing. Notice
that the test bench module does not have any ports of its own. The input and output ports
of the UUT are what are important, and when we simulate the test bench file, we will
examine those signals.

4. Simulate the 2:1 MUX test bench.

(a) Click on the ‘+’ symbol to the left of “ISim Simulator” in the Process window.

(b) Select the 2:1 MUX test bench file in the hierarchy window and then double click
“Simulate Behavioral Model” from within the Process window.
 Laboratory Exercise 1

(c) If there are any errors or warnings, they will show up in the Console window. Correct any
errors and warnings at this time. You may re-run the simulation process once you have fixed
your source code.

(d) The ISim window shown below will open once your design successfully compiles. Take
note of the waveform window in the top-right corner and the Console window at the bottom.
Notice that the test bench exercises the multiplexer through all of the possible input
combinations. Ensure that your design passes all of these tests. Please include a screenshot of
the waveform in you lab write-up along with the console output of the test bench.
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5 Experiment 2

The purpose of this experiment is to design the modules necessary to build our simple 4-bit ALU, while
introducing a level of abstraction available in Verilog. Each component will be tested using ISim with the
provided test benches. You may need to look back at Experiment 1 if you forgot how to perform a procedure
listed below in ISE.

1. Figure 2 illustrates how to connect four 1-bit, 2:1 multiplexers together to create a single 4-
bit, 2:1 multiplexer. This diagram should reflect the circuit you bread-boarded in the previous
lab.

(a) Using the aforementioned diagram and the code below as a starting point, describe a 4-bit,
2:1 multiplexer, which uses the module you created in Experiment 1.

Figure 2: 4-bit wide, 2:1 MUX

‘timescale 1ns/1ps
‘default nettype none
/* This module connects four 1-bit, 2:1 MUXs together to create a single 4-bit, 2:1
MUX*/
module four_bit_mux (Y, A, B, S);
/* declare output and input ports */
//output is 4 -bit wide wire
Input wire [3:0] A,B; // A and B are 4 - bit wide wires
Input wire S; //select is still 1 bit wide
/* instantiate user-defined modules*/
//Write your code here

//you need two more module instantiations here

endmodule
Laboratory Exercise 1

(b) Add the file you just created to your current ISE project.
(c) Copy the appropriate test bench file, “four bit mux tb.v”, into your lab1 directory. As a re-
fresher, the commands to do so may be found below.
>cd $HOME/VLSI/Lab1
>cp /homes/faculty/shared/VLSI/four_bit_mux_tb.v.
Note: If you use the same terminal that you used to do the last copy, you do not need to
execute the first command!
(d) Add the test bench that you just copied over to your ISE project and simulate the logic
behavior as you did in the previous experiment. Please include a screenshot of the waveform
in you lab
2. In the previous steps, we used structural Verilog to describe a 1-bit, 2:1 MUX. Then we used
structural Verilog again to create a 4-bit, 2:1 MUX from our 1-bit MUX module. For the
addition/subtraction unit, we will start with a slightly higher level of abstraction available in
Verilog, commonly referred to as dataflow. The following steps will guide you through the
process.

1. The assign statement in Verilog allows us to describe how data should flow from one wire
to the next using arithmetic and logic operators available in most programming languages.
The operand and result wires can be an arbitrary width; however, the width of each wire
should match the operation being performed. For example, if you are describing a bit-wise
AND operation on two 4-bit wires ( assign Result = A & B; ), the result wire should be 4-
bits in width as well. Using the gate-level schematic for a full-adder illustrated in Figure 3
and the code snippet below as a template, describe a full-adder in Verilog using dataflow
abstraction.
Hint: The full-adder schematic provides suggested intermediate signal names.

‘timescale 1ns/1ps
‘default nettype none
/* This module describes the gate-level model of full adder in Verilog*/
Module full_adder (S, Cout, A, B, Cin);
/* declare output and input ports */
Input wire A, B, Cin;
wire andBCin, andACin;

endmodule

2. Copy over the full-adder test bench file, “full adder tb.v”, from the course directory and add
it to your current ISE project. Simulate the full-adder design and ensure it works properly.
Include a screenshot of waveform in your lab write-up along with the console output from the
test bench.
3. Now that we understand the basics of structural and dataflow Verilog, we can use a mixture
 Laboratory Exercise 1

of the two abstraction levels to create the addition/subtraction unit found in Figure 4. As with
the previous procedures, use the code below as a starting point.

Figure 3: Full-Adder Gate-level Schematic

Figure 4: Addition/Subtraction Unit

Laboratory Exercise 1

4. Copy “add sub tb.v” from the course directory into your lab1 directory and simulate the test
bench. As with the previous simulations, include the waveform and console output of the
test bench simulation in your lab manual.
 Laboratory Exercise 1

6 Experiment 3(Optional)
For this experiment, you will use your new found Verilog skills to create the simple 4-bit ALU described in
the previous lab.

1. Using your corrected block diagram of the 4-bit ALU from the previous lab submission,
create a top-level module with the following interface:

Module four_bit_alu(
Output wire [3:0] Result;
Output wire Overflow;
Input wire [1:0] ctrl;
Input wire [3:0] opA, opB;
/*ctrl | operation
00 | AND
01 | ADD
10 | SUB
11 | OR
endmodule

Add your code here the skeleton is given above

Laboratory Exercise 1

Hint: Your code should instantiate the 4-bit, 2:1 MUX and the addition/subtraction unit which
you have already designed.

2. Copy the 4-bit ALU test bench, “four bit alu tb.v”, file from the course directory and add it
to your current ISE project.

3. Simulate the test bench and add the appropriate material to your lab submission. Demonstrate
your progress to the TA once your circuit simulates properly without errors or warnings.

4. (Honors) In the last lab, we asked that you add a signal to your ALU which is asserted HIGH
when performing a subtraction and A ≥ B. Using the module interface below and a guide,
modify your ALU to include this wire. Simulate your modification with the test bench file,
“four bit alu honors tb.v”.

Module four_bit_alu(
Output wire [3:0] Result;
Output wire Overflow;
Input wire [1:0] ctrl;
Input wire [3:0] opA, opB;
/*ctrl | operation
00 | AND
01 | ADD
10 | SUB
11 | OR
endmodule
Add your code here the skeleton is given above
 Laboratory Exercise 1

7 Post-lab Deliverables
Please include the following items in your post-lab write-up in addition to the deliverables mentioned in the
Policies and Procedures document.

1.Include the source code with comments for all modules you simulated. You do not have to
include test bench code. Code without comments will not be accepted!

2.Include screenshots of all waveforms captured during simulation in addition to the test bench
console output for each test bench simulation.

3.Examine the 1-bit, 2:1 MUX test bench code. Attempt to understand what is going on in the code.
The test bench is written using behavior Verilog, which will read much like a programming
language. Explain briefly what it is the test bench is doing.

4.Examine the 4-bit, 2:1 MUX test bench code. Are all of the possible input cases being tested?
Why or why not?

5.In this lab, we approached circuit design in a different way compared to previous labs. Compare and
contrast bread-boarding techniques with circuit simulation. Discuss the advantages and disadvantages
of both. Which do you prefer? Similarly, provide some insight as to why HDLs might be preferred
over schematics for circuit representation. Are there any disadvantages to describing a circuit using
an HDL compared to a schematic? Again, which would you prefer.

6.Two different levels of abstraction were introduced in this lab, namely structural and dataflow. Provide
a comparison of these approaches. When might you use one over the other?

7. (Honors) Examine the 4-bit ALU test bench code. The test bench actual computes the result it is
expecting from the hardware that it is testing and uses this result to perform a known answer com-
parison. Notice that Overflow detection is done slightly different in the test bench. How is overflow
detection different in the test bench compared to the UUT? Similarly, how is the result computation
different?

8 Important Student Feedback

The last part of lab requests your feedback. We are continually trying to improve the laboratory exercises
to enhance your learning experience, and we are unable to do so without your feedback. Please include the
following post-lab deliverables in your lab write-up.

Note: If you have any other comments regarding the lab that you wish to bring to your instructor’s attention,
please feel free to include them as well.

1.What did you like most about the lab assignment and why? What did you like least about it and why?

2.Were there any section of the lab manual that were unclear? If so, what was unclear? Do you have
any suggestions for improving the clarity?

3.What suggestions do you have to improve the overall lab assignment?

Laboratory Exercise 1

9 Lab 1 Checkoff

ASSIGNED: Week of __/____

DUE: Week of __/____, 10 minutes after start of your assigned lab section.

Name: ____________________________ Enrollment No.: ____________________________

Section: ___________________________

I Understanding of ISE simulator _______ /(20)

II Behavior Simulation & Post Routing Simulation _______ /(15)

III Understanding of Basic of Digital Circuits

1 Combinational _______ /(20)

2 Sequential _______ /(20)

IV Quality of Verilog _______ /(25)

V Complete Simulation _______ /(25)

VI Pin Assignment _______ /(25)

VII Bit FIle generation & Demonstration on Kit _______ /(50)

VIII Hours Spent: __________

IX Total: __________

X Faculty Signature: __________

XI Late Submission: Total Marks -100

XII Final Score _______ /200

Made on 27/11/2017 Amit Kumar New compilation