Energy and Power Engineering, 2013, 5, 64-69
doi:10.4236/epe.2013.53B013 Published Online May 2013 ([Link]
An Analysis of Buck Converter Efficiency in PWM/PFM
Mode with Simulink
Cheng Peng, Chia Jiu Wang
University of Colorado at Colorado Springs, Department of Electrical and Computer Engineering, Austin Bluffs Parkway,
Colorado Springs, USA
Email: cwang@[Link]
Received 2013
ABSTRACT
This technical paper takes a study into efficiency comparison between PWM and PFM control modes in DC-DC buck
converters. Matlab Simulink Models are built to facilitate the analysis of various effects on power loss and converting
efficiency, including different load conditions, gate switching frequency, setting of voltage and current thresholds, etc.
From efficiency vs. load graph, a best switching frequency is found to achieve a good efficiency throughout the wide
load range. This simulation point is then compared to theoretical predictions, justifying the effectiveness of computer
based simulation. Efficiencies at two different control modes are compared to verify the improvement of PFM scheme.
Keywords: PFM; PWM; Buck Converter; Efficiency
1. Buck Converter Background have a relation with input shown below:
Vout = VinD, where D is the duty cycle.
For a buck converter, by varying the duty cycle of the
switch, a desired average voltage output can be achieved.
Figure 1 shows a typical buck converter.
PWM Switching Frequency Selection
A typical synchronous buck circuit using MOSFETs as Frequency is directly related to output ripple. Note that with
a switch is shown in Figure 2. the output voltage ripple assumed to be much smaller
Power Width Modulation (PWM) signal is the most than its average value, most of the inductor current ripple
typical control signal applied on a switch in switching must go through the capacitor. The output voltage ripple
DC converters. It is usually a signal with fixed frequency. can be determined by the following equation.
Inside one period, the signal is high for a specific per-
VOUT (1 D)TSW 2
centage of the period (duty cycle) and then turns off; one
would intuitively predict that the output voltage would VOUT 8 LC
where Tsw is the switching period and fsw = 1/Tsw.
Normally the switching frequency should be set much
higher than frequency of other LC components, ranging
from 250 kHz to 1.5 MHz with feedback loop’s ac char-
acteristics in consideration [1-3]. International Rectifier
uses 600 kHz for their IR 3840 regulator [6]; National
Semiconductor uses 3 MHz fixed frequency for their
LM3677 DC converter [4]. For simulation in this study:
Figure 1. A typical buck converter. Vin = 3.6 V, Vout = 1.8 V, C = 10 uF, L =1 µH. Output
ripple =0.014 V (with output voltage being 1.8 V), we
can have the switching frequency equal to 894.42 kHz.
Further simulation study shows that this is not the opti-
mized frequency to achieve the best conversion effi-
ciency. In the next section it is found that when fre-
quency equals to 1600 kHz the PWM converter achieved
Figure 2. Buck converter with MOSFETs imple- the highest efficiency, with a ripple of 0.05 V. So it is a
menting switches. tradeoff between voltage ripples and efficiency in con-
Copyright © 2013 SciRes. EPE
C. PENG, C. J. WANG 65
clusion. where RESR is the capacitive resistance.
2. PWM Power Loss Analysis 2.2. Switching Losses
In a DC-DC converter, the losses can be classified into Switching losses are frequency dependent losses. It can
two types: load dependent conduction losses and fre- break down into two categories: hard switching loss and
quency dependent switching losses. The recent work in soft switching.
power loss analysis can be seen in literature [7,8].
2.2.1. Hard Loss (overlap loss)
2.1. Conduction Losses As the transistor switches on and off, the voltage and the
During the continuous conduction mode (meaning in- current of the transistor cannot change simultaneously.
ductor current won’t reach down to zero) where the load Thus, the voltage across drain and source of the MOS-
current is relatively large, the main contribution of power FET and the current flowing from drain to source would
losses are the conduction loss of the on-resistance of have a time window during which voltage and current are
high-side (Ron_PFET) and low-side(Ron_NFET) switches and nonzero. Thus, hard switching power loss of a switch can
the series resistance of the inductor and capacitor (RL, be written as
RESR). 1
Pswitching Vin I load [toff ton ] f s
2
2.1.1. Conduction Loss on Switches Here toff is the time taken for the current to reach down
When in operation the upper path and lower path switches to zero when ON gate voltage is canceled and VDS goes
are turned on and off depending on the duty cycle. Hence, to high. ton is the time taken for the current to recover
the average resistance for these switches can be ex- when ON gate voltage is applied and VDS goes low
pressed as the on resistance multiplied by the duty cycles. again. The losses due to each action are referred to as
The on-resistance in one switching cycle can be written turn on loss and turn off loss, respectively.
as:
Rswitches _ on Ron _ PFET D Ron _ NFET (1 D) 2.2.2. Soft Loss (gate drive loss)
Then the conduction loss due to on-resistance inside Soft loss is mainly due to the parasitic capacitors at the
MOSFET can be written as: switching nodes. Since the switch size has to be rela-
tively large to handle the load current with proper on-
Pswitches _ on [ Ron _ PFET D Ron _ NFET (1 D)] I out
2
resistance, the capacitance associated with it at the
switching node could be quite significant.
2.1.2. Conduction Loss on Inductors and Capacitors The parasitic capacitance at the switching node, Ctotal
Non-ideal inductor has series resistance consuming extra can be express as follows:
power when passing through current. As mentioned be- Ctotal Cox Cgb Cds Csb Cgd Cgs Cdb
fore the average inductor current is also the same as the
load current in Steady-state, the conduction loss can then Thus, the gate driver loss for each stage can be intui-
be written as the product of this current squared and the tively given by
resistance. Industrial experience shows however that Pgate_drive = CtotalV2fs
current variation of the inductor also contributes to the Under the continuous conduction mode, the most
loss. A more accurate empirical equation of inductive dominate switching loss is due to the hard switching loss,
loss is given as follows: since it is proportional to both current and switching fre-
quency. However, under the light load condition, the
PL RL ( I load I inductor 2) 2 ,
most dominated switching loss is due to the gate drive
where RL is the inductive resistance, ILOAD is the load loss since the current is small.
current and ∆Iinductor is the inductive current variation.
∆Iinductor can be derived as: 2.3. PWM Loss Simulink Verification
Vin D D ' Ts Figure 3 shows the PWM controlled buck converter im-
I inductor
2L plemented in Simulink. Figure 4 shows power loss of
For capacitor, equivalent-series resistance (ESR) is the this converter. Figure 5 shows the conversion efficiency
main cause for power loss. The empirical capacitive loss versus switching frequency.
equation is given as follows
3. PFM Control Mode Basic Theory
PC (I inductor 3) 2 RESR ,
In order to tackle the dissatisfactory efficiency at low load,
Copyright © 2013 SciRes. EPE
66 C. PENG, C. J. WANG
Figure 3. The PWM Buck Converter in Simulink.
Conversion Efficiency VS Load current Conversion Efficiency VS Switching frequency
90 0.92
0.91
85
0.9
Conversion Efficiency (%)
Conversion Efficiency (%)
80 0.89
0.88
75
0.87
70 0.86
0.85
65
0.84
60 0.83
0 200 400 600 800 400 800 1200 1600 2000 2400 2800 3200 3600 4000
Load current (mA) Switching frequency (kHz)
Figure 4. Conversion efficiency in a buck converter in Figure 5. Conversion efficiency in a PWM buck converter
PWM control mod with variant load current. vs. switching frequency.
Copyright © 2013 SciRes. EPE
C. PENG, C. J. WANG 67
we need a control scheme with lower switching frequency The detail equations are omitted in the paper due to space
or conduction current. Note also the minimum frequency limitation.
is needed to maintain a demanded output ripple. Pulse
Frequency Modulation (PFM) scheme is designed to suf- 3.3. PFM Loss Simulink Verification
ficiently decrease the switching frequency and conduc-
LM3677 is a DC converter from National Semiconductor
tion current at light load while maintaining required out-
using PFM/PWM control mode. In this device output
put voltage ripple [5].
voltage thresholds are set between ~0.2% and ~1.8%
3.1. Control Scheme above nominal PWM output voltage. In order to compare
conversion efficiency under same criteria, The PFM
Unlike PWM where the P gate and N gate is controlled mode also has to set the same output ripple the same as
with duty cycle to be on and off, in PFM they are con- the one in PWM (1.77 V to 1.82 V). Also the typical
trolled by Thresholds. To be specifically, the thresholds peak current in PFM mode is:
used in PFM control are High Vout Threshold, Low Vout
Threshold, Mode Transit Threshold and Inductor Current I peak 112mA Vin / 20
Peak Limit. Figure 6 shows how this control scheme
In our study, Vin = 3.6 V. The result is 192 mA. With
advances in time axis. PFM scheme is designed for light
load so when the load current increases beyond a certain LM3677 as benchmark, the thresholds of simulation in
point, the output voltage would be drawn below a thresh- this study are set to be: High Vout Threshold = 1.814 V;
old, which is shown in the figure as “Mode Transit Low Vout Threshold = 1.809 V; Inductor peak current
Threshold”. When this happens, the circuit switches back limit = 200 mA; Mode Transit Threshold = 1.804 V. Fig-
to PWM mode to keep up with the load demand. ure 7 shows the PFM controlled buck converter in Simu-
link.
3.2. PFM Power Loss Analysis
4. Loss and Efficiency Comparison
The reason for loss saving in this control mode is mainly
due to the “sleep phase”. During this phase both switches The blue curves dotted with x are PWM mode, red
are turned off, the source for output power is all from the curves dotted with o is PFM mode. It’s easily seen that
capacitor charge, saving all losses could have occurred the loss in PFM is much lower than that in PWM mode at
on switches and the inductor. During the PFM operation, light load (10 mA - 40 mA), and rapidly increases with
the output is being charged as needed. Thus, the average the load going high. Figure 8 shows the loss comparison
inductor current and load current would be smaller than curves with all losses summed up.
the ripple current and the conduction loss would only The efficiency is measured with load from 10 mA -
occur during “pump phase”, resulting in less power loss. 110 mA as shown in Figure 9.
Figure 6. PFM mode operation and transfer to PWM mode.
Copyright © 2013 SciRes. EPE
68 C. PENG, C. J. WANG
Figure 7. Shows the PFM controlled buck converter in Simulink.
PWM and PFM overall loss compare
0.11
0.1
0.09
0.08
Overall loss (W)
0.07
0.06
0.05
0.04
0.03
0.02
0.01
10 20 30 40
Load current (mA) Figure 9. Efficiency comparisons between PWM and PFM
mode control. (PWM is indicated by x; PFM is indicated by
Figure 8. Shows the loss comparison curves with all losses o).
(PWM is indicated by x; PFM is indicated by o).
From the graph we can see that the efficiency im- 5. Conclusions
provement at light load varies from 0 - 30%. Note in Computer based simulation proved the effectiveness of
PWM the frequency has been fine-tuned at 1600 kHz so theoretical prediction on conversion power losses. The
the improvement is pretty significant. proposed PFM control scheme is also verified to have a
Copyright © 2013 SciRes. EPE
C. PENG, C. J. WANG 69
significant improvement on conversion efficiency at light Converter for Ultra Low Voltage Circuits National
load (as high as 30%). Semiconductor,” Vol. 7, 2007.
[5] K. B. Naima, C. Wen, A. Prashant and J. Elec Electron,
“FPGA-Based Combined PWM-PFM Technique to Con-
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