Scribd
Upload
97 views2 pages

Verified The Logic of Scan-Chain and LFSR Using Verilog Code. Calculated The Area Over-Head For Scan-Chain

Siddhartha Sharma has worked as a layout designer since January 2016. His core competencies include layout design and he has experience using tools like Cdesigner, Modelsim, and Laker. He has worked on projects involving PLL and SRAM dual port design in 28nm CMOS technology. For the PLL project, he performed layout design of a charge pump and verification checks. For the SRAM project, he worked on bitcell layout and schematic, write circuitry, and scan-chain logic. He is proficient in analog layout techniques and understands CMOS fabrication processes. He received a B.Tech in ECE from KEC Ghaziabad in 2015 with a 7.0 CGPA

Uploaded by

SiddharthSharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
97 views2 pages

Verified The Logic of Scan-Chain and LFSR Using Verilog Code. Calculated The Area Over-Head For Scan-Chain

Siddhartha Sharma has worked as a layout designer since January 2016. His core competencies include layout design and he has experience using tools like Cdesigner, Modelsim, and Laker. He has worked on projects involving PLL and SRAM dual port design in 28nm CMOS technology. For the PLL project, he performed layout design of a charge pump and verification checks. For the SRAM project, he worked on bitcell layout and schematic, write circuitry, and scan-chain logic. He is proficient in analog layout techniques and understands CMOS fabrication processes. He received a B.Tech in ECE from KEC Ghaziabad in 2015 with a 7.0 CGPA

Uploaded by

SiddharthSharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

SIDDHARTHA SHARMA

Email Id : ceedarth@[Link]
cell no. : 9958327447

CORE COMPETENCIES
Layout Design.

WORK EXPERIENCE
Working since January 2016.

TOOLS & TECHNOLOGIES Cdesigner , Modelsim, Laker and Galaxy Custom


TOOLS
Designer from Synopsys.
TECHNOLOGY Hspice for circuit simulations.
28nm CMOS technology

PROJECTS DETAILS:-

PROJECT 1 – PLL.
TECHNOLOGY - TSMC CMOS28
ROLES AND RESPONSIBILITIES:

Layout design of Charge Pump.


Performed Physical verification check by DRC run checks using Hercules from Synopsys .
Performed Physical verification check LVS run checks Hercules from Synopsys .
Post layout extraction using StarRC.

PROJECT 2.– DESIGN OF SRAM DUAL PORT.


TECHNOLOGY - TSMC CMOS28
ROLES AND RESPONSIBILITIES:

Worked on layout and schematic of Bitcell.


Worked on layouts and Schematic for Write circuitry
Done the circuit level simulations for Write circuitry.
Calculation of parameter such as Write Margin of bit
cell. Build the logic for Scan-chain and LFSR.
Verified the logic of Scan-chain and LFSR using verilog
code. Calculated the area over-head for scan-chain.
Worked on layouts and schematic of Scan-chain and
LFSR. Also done the circuit level simulation for Flip-flops.
Layout design of Op-amp.
Responsible for calculating the Gate capacitance for NMOS and PMOS cell by layout, used
for calculating the delays in the circuit.
TECHNICAL EXPOSURE
Understanding of CMOS Fundamentals and fabrication process.
Understanding about "Sharing & Fingering Techniques".
Analog techniques to implement device matching and signal balancing.
Standard analog layout techniques and good understanding of physical, electrical aspects of
layout. Understanding of reliability physics including Electro-migration,Latch-up, Antenna Effect, IR
Drop, LOD Effects.
Proficiency with industry-standard layout and verification tools in a Linux
environment. Self-sufficiency in debugging complex verification failures.
Created the P-cell using Python.

EMPLOYMENT HISTORY
Customer/Client Duration
Organization Masamb Electronics Systems Jan’16- Till date
Internal
Pvt.
Ltd

EDUCATIONAL QUALIFICATION

Qualification/ Institution Year of Passing CGPA

Degree [Link](ECE) KEC, Ghaziabad 2015 7.0

You might also like