Mixed-Signal Design and Automation Methods

混合信号电路设计与自动化方法

Lecture 8
gm/ID Sizing Method

Prof. Guoyong Shi

[email protected]
Dept of Micro/nano-electronics
Shanghai Jiao Tong University
Fall 2015
 Preface
• This lecture was based on the following paper:

– F. Silveira, D. Flandre, and P. G. A. Jespers, “A gm/ID based

methodology for the design of CMOS analog circuits and its
application to the synthesis of a silicon-on-insulator
micropower OTA,” IEEE J. Solid-State Circuits, vol. 31, pp.
1314–1319, Sep. 1996.

2015-12 Lecture 8 gm/ID slide 2

 Outline
• Intrinsic gain stage
• gm/ID in different regions
• gm/ID versus normalized current (ID/(W/L))
• gm/ID sizing procedure
• Experimental result
• SOI technology for low-power circuits
• Summary

2015-12 Lecture 8 gm/ID slide 3

 Tradeoff btw Power & Speed
• CMOS analog circuits traditionally work in strong
inversion (saturation)
• Weak inversion region  minimum power
consumption; but slow

• Moderate inversion  good compromise in power

and speed (future design interest)

• Design challenges:
– Requiring both low power and high speed

2015-12 Lecture 8 gm/ID slide 4

 Traditional Design Methodology
• Traditional optimization approaches  SPICE plus
numerical optimization software
– Disadvantage: lack of design insights
• Main stream methods emphasize “strong inversion”;
• Micropower design techniques exploit known “weak
inversion” models.
• Symbolic or simple hand-calculation methods 
better insights,
– But lack simple and accurate hand models for moderate
inversion

2015-12 Lecture 8 gm/ID slide 5

 The gm/ID Methodology
• One single model that works in all operation regions.
• Focused on gm/ID ratio versus the normalized current
ID/(W/L)
– the normalized current ID/ (W/L) is characterized experimentally
– or fitted with simple analytical models

• Helps design in moderate inversion for low-power

circuits
– Offering good compromise between speed and power.;
– power lower but speed not bad!

2015-12 Lecture 8 gm/ID slide 6

 Motivation of gm/ID
• gm/ID is a measure of the efficiency to translate
current (i.e., power) into gm (i.e., gain).
– The greater gm/ID, the greater gm is for a fixed ID.
– gm/ID is interpreted as a measure of the “gm enhancement
efficiency”.
• It is strongly related to the performance of analog
circuits.
• It also gives an indication of the device operating
region.
• It can be used for transistor sizing.

2015-12 Lecture 8 gm/ID slide 7

 Intrinsic Gain Stage (I.G.S.)

ID
Vin Vout
M vout
C vin g m vin gd C

The common
The equivalent small-signal circuit
source transistor
M is in saturation

2015-12 Lecture 8 gm/ID slide 8

 GBW
Gain-Bandwidth Product (GBW)

Vout ( s ) = H ( s )Vin ( s )
vin g m vin gd C vout

vout gm
DC gain: g m vin = − g d vout H DC = H (0 ) = = −
vin gd

High freq gain:

vout gm
g m vin = − jωCvout H ( jω ) = = −
vin jωC

 At high frequencies, most of the current flows by the capacitor C.

2015-12 Lecture 8 gm/ID slide 9

 Channel Length Modulation

gd
Early voltage ID
ID
gd =
VA
VA VDS
vout gm
= − The Early voltage VA controls the
vin gd transistor small-signal output
conductance, gd = ID/VA.

vout g g
ADC =
H (0 ) = =
− m =
− m VA
vin gd ID

2015-12 Lecture 8 gm/ID slide 10

 GBW (cont’d)
g mVA A( dB )
H (0 ) = − ωc : corner freq
ID
gm
ADC = VA
vout g ID
H ( jω ) = = − m
vin jωC at corner −20dB / dec
freq
0dB ω
= =
ADC=
H ( s ) s 0=
H (s) s jωc ωc g
ωT = m
C
ωT : transition freq
g mVA g
= m
ID ωc C
gm
ωT ω=
= c ADC
VA 1 ID C
= ωc =
I D ωc C CVA
GBW

2015-12 Lecture 8 gm/ID slide 11

 Calculation of gm/ID
The expression for gm/ID is derived as follows:
Called normalized drain
current
 I D 
∂ ln  W 
 ( L ) 
ID
gm 1 ∂I D ∂ ln I D  I ≡
= = =
I D I D ∂VG ∂VG ∂VG
( WL )

ID normalized by the
transistor size.

The derivative is maximum in the weak inversion (WI) region

where the dependence of ID versus VG is exponential.

 V   ID  VG
I D = I 0 exp  G  ln  =
 nU T   I0  nU T

2015-12 Lecture 8 gm/ID slide 13

 Quadratic MOS Models
The connections between ID, the W/L ratio, and gm can be derived
from the transistor large-signal model.

The classical MOS model is defined for the three regions:

1) Strong inversion region (Quadratic Model):

• When Vov = (VG-Vth) > 0.2V.

2) Moderate inversion region;

3) Weak inversion region: Once the current approaches ID,min (see the
lecture on EKV), W/L must be increased fastly to further increase the
DC gain.

2015-12 Lecture 8 gm/ID slide 14

 Quadratic model in Strong Inversion
The quadratic expression of ID for a MOS transistor in saturation:

(VG − Vth )2 n is the slope W

ID = β factor ≈ 1 β = µ Cox
2n L

∂I D V − Vth 2β I D W ng m2 1
=
gm = β G = = .
∂VG n n L 2 µ Cox I D

We also have

2β I D β gm
=
2
=
gm = (VG − Vth ) Indep. of (W/L)
n n I D (VG − Vth )

ID is proportional to b (hence W), so is gm.

2015-12 Lecture 8 gm/ID slide 15

 (cont’d)
2
W ng m2 1 n W
g n  gm 
2
= . = = L
. m
. 
L 2 µ Cox I D I D 2 µ Cox I 2 µ Cox  I D 
2
D

gm 2 µ Cox 1
=
ID n ID W
L

gm/ID is inversely proportional to the sqrt of the normalized ID.

2015-12 Lecture 8 gm/ID slide 16

 Relation in strong inversion Approx const in
strong inversion
W ng m2 1 W  ng m2 
= . =
L 2 µ Cox I D log  log  − log I D
L  2 µ Cox 

Strong inversion
asymptote

log(W/L)

Weak inversion
asymptote

log(ID) slide 17
2015-12 Lecture 8 gm/ID
 ID  small
g mVA
ADC = (derived for the
ID
Intrinsic Gain Stage)

• It seems that the DC gain would increase to infinite as the drain

current goes to 0.

• However, as the current diminishes, the transistor enters

moderate and weak inversion, where the quadratic model for the
drain current fails.

2015-12 Lecture 8 gm/ID slide 18

 Weak Inversion
The drain current in weak inversion is given by the exponential I-V
relation:

∂I D i.e., gm/ID is
 V  =
gm =
ID
I D = I 0 exp  G  approx.
 nU T  ∂VG nU T const in
weak
I D ,min = nU T g m inversion.

where n is the subthreshold slope factor and UT the thermal voltage.

In weak inversion, the drain current ID alone determines gm,

which in turn determines the GBW.

gm
GBW π fT
= 2= (for I.G.S.)
C
2015-12 Lecture 8 gm/ID slide 19
 Moderate Inversion Region
The candidate model for moderate inversion is (see Jespers 2010,
Chapter 4):
W ng m2 1
=
L 2 µ Cox ( I D − I D ,min )

The expression is valid in all regions, from strong to weak inversion.

Exercise: Design an I.G.S. with

• load C = 1 pF;
• transition frequency fT = 100 MHz;
• µCox = 4x10-4 AV2 ;
• slope factor n = 1.2;
• Early voltage VA = 10V .

2015-12 Lecture 8 gm/ID slide 20

 Figure
Plot of aspect ratio W/L vs ID of an (ideal) Intrinsic Gain Stage.
The numbers besides the RED circles show the Overdrive Gate Voltage
Vov = (VG – Vth).

This figure displays

(W/L) vs ID
achieving the
desired GBW (i.e.,
const fT or gm).

gm EKV model
ADC = − VA
ID

for ID large

IDmin
log ADC =log( − g mVA ) − log I D

(gm ~ const)

2015-12 Lecture 8 gm/ID slide 21

 W/L versus ID (See comments next page)

VOV

gm const
Strong inversion
approx.
EKV model

DC gain

Weak inversion approx. VOV > 0.2 V

2015-12 Lecture 8 gm/ID slide 22

 Comment on the Figure
We see that the DC gain varies like the reciprocal of ID;
 Smaller drain current, larger DC gain.

The largest DC gain is arrived at when ID reaches the minimum

ID,min.

The DC gain is approximated by the equation considering Early

voltage: gm
ADC = − VA
ID

When =
I D I=
D ,min g m nU T
 the max DC gain: VA
ADC ,max = −
nU T

2015-12 Lecture 8 gm/ID slide 23

The thin-film SOI transistors (n=1.1) has increased subthreshold slope (due to
smaller n), giving a maximum value of gm/ID of about 35 while only 25 for bulk
transistors (n=1.5).
gm/ID is approx. const in
weak inversion.
higher
gm/ID
for SOI

Measured
gm/ID becomes quadratic
in strong inversion, then
becoming almost linear in
deep strong inversion (due
Calculated
to velocity saturation).

Calculated and measured gm/ID vs ID/(W/L) for bulk transistors and thin-film
fully-depleted SOI transistors.
2015-12 Lecture 8 gm/ID slide 24
 Observations
• gm/ID decreases when the normalized ID moves toward the
strong inversion region.
• For the same gm/ID, I,p is lower than I,n due to the mobility
difference.
• Hence, requiring larger W/L for pMOS to achieve an equal ID.

• Hence, gm/ID is also an indicator of the transistor operation

region.

• Both gm and ID are proportional to size;

• but gm/ID is size independent.
• Once any two values among gm/ID, gm, and ID are given, we
can determine the aspect ratio W/L.

2015-12 Lecture 8 gm/ID slide 25

 gm/ID vs normalized current
• The normalized current (I = ID/(W/L)) is independent
of the transistor size.
• The relationship between gm/ID and I is a unique
characteristic for one type of transistors.
• However, this statement has to be revised when dealing with short
channel transistors.

• The characteristic of (gm/ID) vs I can be explored

extensively during the design phase
• The actual gm/ID vs I can be obtained by either
analytical method (fitting) or measurement.

2015-12 Lecture 8 gm/ID slide 26

 gm/ID Characterization
• Two characterization methods: semi-empirical or
model-driven.
• 1) Semi-empirical: it makes use of real
measurements or data derived from advanced MOS
models.
• 2) Model-based: it applies simple models with
reliable analytical expression.
– The basic EKV model is a candidate but not perfect;
– The EKV parameters are allowed to vary with bias
conditions and gate lengths.

2015-12 Lecture 8 gm/ID slide 27

 gm/ID Characterization
• In order to take into account of process variations,
• it is more appropriate to consider averaged curves
which are representative of a large number of
transistors

2015-12 Lecture 8 gm/ID slide 28

 Accurate Reference Models
• BSIM is a widely used state-of-the-art model
available in the public domain.
– It is based on threshold voltage formulations;
– But has weaknesses (model inaccuracy) in moderate
inversion.

• PSP model from Penn State University and Philips

(now NXP) is considered the more accurate
industrial standard.
– Based on the surface potential model (like the Charge Sheet
Model of EKV).

2015-12 Lecture 8 gm/ID slide 29

 gm/ID Sizing Procedure

2015-12 Lecture 8 slide 30

 gm/ID Sizing Procedure
We derived from the quadratic model:
gm 2
= gm ~ ID ~ W
I D VGS − Vth

 (gm/ID) is independent of the gate width (W)

•Determine gm according to (GBW = fT): gm = 2π fT C

*
g 
•Determine ID by the const gm/ID equation: I D = gm  m
I 

 D

The reference ratio (gm/ID)* is obtained from a similar device

whose W* and L* are known.

•Determine the device size (W) by the proportionality btw ID and W:

ID
W = (W )*
( ID )
*

2015-12 Lecture 8 gm/ID slide 31

 The reference (gm/ID)*
The reference (gm/ID)* is defined by:

*
 gm  1 dI D * d
=
  = log( I *
D )
 I D  I D dVG dVG
*

Two typical methods:

1. Semi-empirical gm/ID sizing method: Deriving the reference
(gm/ID)* from experimental ID(VGS) characteristics (typically from
advanced models such as BSIM or PSP).

2. Model-based method: Deriving (gm/ID)* from analytical large

signal model adequately accurate by parameter fitting (e.g., EKV
model).

2015-12 Lecture 8 gm/ID slide 32

 Application to OTA Synthesis

Cascode OTA, CMOS-SOI technology

2015-12 Lecture 8 slide 33

 Application
Synthesize a cascode OTA by the gm/ID method:
VDD

I0
M8 M9 ID2

M1 M 2 M 10 VB p
VIN − VIN +
ID1
VBn 2 M 11 M7 CL
VBn
M5 M3 M4 M6
1:1 1: B
B is the current
VSS
mirror gain
OTA schematic (to be
implemented CMOS-SOI)
2015-12 Lecture 8 gm/ID slide 34
 OTA Synthesis
• Assume total supply current is Itot = 2 mA, load
capacitor is CL = 10pF, and supply voltage VDD = 3 V.
• Design to achieve the best performance of:
– Open loop dc gain (ADC),
– Transition frequency (fT),
– Phase margin (PM), and
– Slew rate (SR)

• It is straightforward to take into account of other performance

aspects (like noise or common mode rejection) as long as they
are directly related to the current and small-signal parameters.
• For large-signal performance such as signal swing, an “ID vs
VG” or “gm/ID vs VG” relationship is required.

2015-12 Lecture 8 gm/ID slide 35

 gm/ID Design Flow
I tot (= 2 µ A) B (= 2)

Performance
fT

Evaluation
( g m / I D )1 (= 28)
( g m / I D ) 2 (= 30) A0
gm/ID vs
ID/(W/L) ( g m / I D )3 (= 8) SR

Transistor
(W / L) Lengths CL (= 10 pF )
Early
voltage

(Cox , C j ,) Technology

W,L data

SPICE or
Symbolic Accurate fT
Simulation
Highlighted are the data to be
provided by the designer.
Change B,
Phase Margin < PM_min? gm/ID or L
values

2015-12 Lecture 8 gm/ID slide 36

 OTA Synthesis
The DC gain can be derived as:

 gm   gm  1 (to be derived next)

ADC =  
 D 1  D  2
I I 1 1
+
VA6 ⋅ VA7 VA9 ⋅ VA10

where (gm/ID)1 is the ratio of the input transistors and

(gm/ID)2 is the ratio of the cascode transistors.
VA6,7,9,10 are Early voltages.

The Early voltages are considered proportional to the transistor

length with a typical constant proportionality of 7V/um. (In the paper
L is in the rage of 3 to 12 um.)

2015-12 Lecture 8 gm/ID slide 37

 Derivation of DC Gain
 gm   gm  1
ADC =  
 D 1  D  2
I I 1 1
+
VA6 ⋅ VA7 VA9 ⋅ VA10
VDD
pMOS cascode
stage
I0 V V
Rout , p ≈ g m10 rd 9 rd 10 =
g m10 A9 A10
M9 ID2I D2
M8
ID2
(see appendix)
M1 M 2 M 10 VB p
VIN − VIN +

ID1
M 11 CL
VBn 2 M7
VBn
M5 M3 M4 V V
M6 Rout ,n ≈ g m 7 rd 6 rd 7 =
g m 7 A6 A7
1:1 1: B I D2I D2
nMOS cascode
VSS stage
2015-12 Lecture 8 gm/ID slide 38
 Derivation (cont’d)
V V V V
Rout , p ≈ g m10 rd 9 rd 10 =
g m10 A9 A10 ; Rout ,n ≈ g m 7 rd 6 rd 7 =
g m 7 A6 A7
ID2 ID2 ID2 ID2

VA9VA10 VA 6VA 7
Rout Rout , p  Rout ,n ≈ g m10  gm7
ID2 ID2 ID2 ID2

g m 7.10 1
= g m=
7,10 g=
m7 g m10
VA 9VA10 + VA 6VA 7
1 1
ID2 ID2
gain of 1st stage

g m1 g m 7,10 1 Assuming current

=
ADC g=
m1 Rout mirror ratio from the
VA 9VA10 + VA 6VA 7
1 1
ID2 ID2
input stage to the
cascode stage is 1:1.
 gm   gm  1
=   
 D 1  D  2 VA 9VA10 + VA 6VA 7
1 1
I I

2015-12 Lecture 8 gm/ID slide 39

 (cont’d)
B  I D1 B ⋅ g m1 1st order
SR = fT =
CL 2π ⋅ CL approximation of fT

where B is the current mirror ratio, ID1 is the current of

the first stage, and gm1 is the transconductance of the
input transistor.

Set B = 2 in the paper.

The max B value is limited by its influence on the OTA

stability.

fT is also proportional to gm/ID, given fixed ID.

2015-12 Lecture 8 gm/ID slide 40

 Sizing Procedure for the OTA
1. Determine the drain current of each transistor
according to the total supply current and the current
mirror ratio B (= 2).
2. Choose gm/ID accordingly to their effect on the OTA
performance,
3. Determine the normalized current according to the
experimental curve of (gm/ID) vs I.
4. Calculate W/L for each transistor.

2015-12 Lecture 8 gm/ID slide 41

 Sizing the OTA
The total current is divided into four
branch currents (one branch doubled):

I tot = 2 µ A I=
1 I=
2 I=
3
2µ A
5= 0.4 µ A; I 4 = B ⋅ I 3 = 4 µ5 A = 0.8µ A
VDD
The gm/ID values are determined
after design space exploration
I0 (optimizing tradeoff btw dc gain and
5 9.5 fT for a given PM).
M M9 6
6 8 156
156
3
657.5
 gm   gm 
 = 28;
3
   = 30;
M1 M 2 3
M 10 VB p
I1 VIN − VIN +  I D 1,2  D 7,10
I
I4
VBn 2 I2 I3 CL
94 187.5
VBn (correspond to operation in
M 11 3 3 M7 the moderate inversion region
3.5 3.5
12
close to W.I.)
3.5 12
12 M5 M3 M4 M6 7

1:1 1: B
12 The current mirror
transistors (M3,4,5) are  gm 
VSS sized in S.I. to guarantee   = 8;
B=2 good matching and noise  D 3
I
properties.
2015-12 Lecture 8 gm/ID slide 42
 Choice of gm/ID
• The dc gain is proportional to gm/ID  gm/ID higher
better.
• fT is proportional to gm, hence gm/ID (if ID is fixed).
 also gm/ID higher better.

• However,
• The max gm/ID is limited by the weak inversion value
– about 35 V-1 for thin-film fully-depleted SOI MOS (higher);
– about 25 V-1 for bulk CMOS
• Also limited by the stability requirement
– because increasing gm increases the transistor sizes (W),
(hence, the parasitic caps), reducing the phase margin.

2015-12 Lecture 8 gm/ID slide 43

 Looking up I from Curve

30
28
For nMOS, I » 10-8
for gm/ID = 30. gm
For pMOS, I is ID
smaller.

For nMOS, I » 10-6

for gm/ID = 8.
For pMOS, I is
smaller.
about 100x

2015-12 Lecture 8 gm/ID slide 44

 Sizing Details - 1
1) Sizing the mirror transistors ...
M8 (pMOS) sized M9 (pMOS) sized to
to 10/12 = 5/6 2xW8 = 10/6 (9.5/6
5 9.5 in the paper)
6 I0 6

M8 M9

I= I= I= 0.4 µ A; M1 M 2 M 10
1 2 3 VIN − VIN + I 4 =2 ⋅ I 3 =0.8µ A
I1 I4
I2 I3
M6 (nMOS) sized to
M 11 M7 2xW4 = 7/12

M5 M3 M4 M6 M3,4,5 sized to
1:1 1: B 3.5/12
7
3.5
12
12
gm W I D 4 × 10−7
=8 I  = 10 A −6
= = −6
= 0.4
ID L I 10
2015-12 Lecture 8 gm/ID slide 45
 Sizing Details - 2
2) Sizing the cascode transistors (M7, M10) ...
I 4 =2 ⋅ I 3 =0.8µ A
I=
1 I=
2 I=
3 0.4 µ A;

I0
M10 (pMOS)
M8 M9 sized larger to
657.5
3
657.5/3 = 219
M1 M 2 M 10
VIN − VIN +
I1 I4
I2 I3
gm M7 sized to
M 11
187.5
3 M7 = 30 187.5/3 = 62.5
ID
M5 M3 M4 M6
1:1 1: B
W I D 8 × 10−7
−8
I  = 10 A = = = 80
L I 10−8
2015-12 Lecture 8 gm/ID slide 46
 Sizing Details - 3
3) Sizing the input transistors (M1,2) and M11 ...

I=
1 I=
2 I=
3 0.4 µ A;

I 4 =2 ⋅ I 3 =0.8µ A
I0 M1,2 sized to
156/3
M8 156
M9
M111 sized 3 W I D 4 × 10−7
to 94/3 = = = 50
M1 M 2 M 10 L I  8 × 10−9
VIN − VIN +
I1 I4
94 I2 I3
3
M 11 M7
I  ≈ 8 × 10−9 A (looked up
from curve)
M5 M3 M4 M6
1:1 1: B
gm
= 28
ID
2015-12 Lecture 8 gm/ID slide 47
 Summary of Transistor Sizes

The transistor lengths are

determined by a trade-off btw area TABLE Ⅰ
OTA Transistor Dimensions
and stability, and dc gain
W L Effective W/L
(dependence of Early voltage on L).
M1 156 3 57.6
VA ~ 7 (V/um) L empirically for L
M2 156 3 57.6
3~12um.
M3 3.5 12 0.26
M4 3.5 12 0.26
M5 3.5 12 0.26
M6 7 12 0.52
M7 187.5 3 69.3
M8 5 6 0.79
M9 9.5 6 1.58
M10 657.5 3 243.3
M11 94 3 34.6

2015-12 Lecture 8 gm/ID slide 48

 Experimental Result
• The sized OTA was realized in the 3-um CMOS-SOI process.

TABLE Ⅱ. Calculated, simulated and measured results of OTA

Synthesis Prog. HSPICE Measurements Notes

(gm/ID)1 (1/V) 28 29.4 28.3
(gm/ID)2 (1/V) 30 31.6 30.5
A0 (dB) 103.9 105.5 103
fT (kHz) 324 336 @CL=10pF
PM (deg.) 72.5 72 @CL=10pF
fT (kHz) 261* 270* 271* @CL=12.3pF
PM (deg.) 63.8* 63* 60* @CL=12.3pF
SR (V/us) 0.11 0.09 0.1 @CL=12.3pF
Output swing (Vpp) 2.02 2.2 1.93 @Vdd=3V

HSPICE uses level 34 model with a set of parameters optimized to fit the
SOI MOSFET characteristics.
2015-12 Lecture 8 gm/ID slide 49
 DC Gain Estimation
The open-loop dc gain can be estimated as follows:

g  g  1
ADC =  m   m 
 I D 1  I D  2 1 1
+
VA6 ⋅ VA7 VA9 ⋅ VA10

 gm   gm  −1 VA ≈ (7V µ m) ⋅ L

−1
 = 28V ;   = 30V ;
 I D 1  I D 2

L6 = 12; L7 = 3; L9 = 6;
1 L10 = 3 um
ADC= 49 × ( 28 )( 30 )
1 1
+
12 × 3 6 × 3

2
= 18 × 49 × ( 28 )( 30 ) × = 493,920 20log10 ( ADC ) = 113.8 dB
3
~ HSPICE 105.5 dB
2015-12 Lecture 8 gm/ID slide 50
 Comparison to Other Synthesis Methods
TABLE Ⅲ. Comparison of results of gm/ID based synthesis with conventional
strong inversion (SI) and weak inversion (WI) synthesis

gm/ID SI SI WI WI
method synthesis. real synthesis. real

(gm/ID)1 (1/V) 28 28 18.7 35 30

(gm/ID)2 (1/V) 30 30 19.7 35 30.5
A0 (dB) 103.9 103.9 96.7 107.1 104.6
fT (kHz) 324 351 236 395 344
PM (deg.) 72 84 86 64 68
W/L input pair 57.6 7.7 7.7 120.9 120.9
W/L cascode n 69.3 6.47 6.47 93.5 93.5

Die area W/L cascode p 243.3 17.3 17.3 241.7 241.7

ΣW×L (um2) 4900 1359 1359 6185 6185

By strong inversion (SI) synthesis, it overestimates fT by about 50% and the gain by about 7dB.
By weak inversion (WI) synthesis, it overestimates fT by 15% and the die area by 25%.

2015-12 Lecture 8 gm/ID slide 51

 Comments on the comparison
• The strong inversion (SI) synthesis extends quadratic
expression to moderate inversion, this will underestimate
transistor size (W/L), hence amplifier area.

• The weak inversion (WI) synthesis considers the exponential

approximation for ID versus VG, it predicts the gm/ID equals to
35, independent of the current. The ID/(W/L) cannot be
determined, it is chosen to guarantee weak inversion operation.

• Using the transistor sizes provided by the SI and WI synthesis,

then referring to the real gm/ID versus ID/(W/L) data, the
resulting estimations are listed as “SI real” and “WI real”.

2015-12 Lecture 8 gm/ID slide 52

 Summary
• gm/ID creates a connection btw the transconductance gm (a
small-signal quantity) to the drain current ID (a large-signal
quantity).

• The gm/ID methodology provides a unified sizing procedure for

MOS devices from the strong to the weak inversion region.

• The gm/ID sizing methodology applies as long as the widths are

large enough so that the lateral effects can be ignored,
– A condition that holds with most CMOS analog circuits.

• The OTA sized with this methodology results in lower current

consumption with increased gain given a bandwidth.

2015-12 Lecture 8 gm/ID slide 58

 References on gm/ID
• F. Silveira, D. Flandre, P. Jespers, “A gm/ID based methodology
for the design of CMOS analog circuits and its application to
the synthesis of a silicon-on-insulator micropower OTA,” IEEE
J. Solid-State Circuits, vol. 31, no. 9, Sept 1996, pp. 1314–1319.
• P. G. A. Jespers, The gm/ID Methodology, A Sizing Tool for
Low-Voltage Analog CMOS Circuits, The Semi-empirical and
Compact Model Approaches, Springer, Heidelberg, 2010.
• D. M. Binkley et al, “A CAD methodology for optimizing
transistor current and sizing in analog CMOS design,” IEEE
Trans. CAD, vol. 22, no. 2, Feb. 2003, pp. 225-237.
• D. M. Binkley, Tradeoffs and Optimization in Analog CMOS
Design, Wiley, Chichester, England, 2007.
• A. Girardi, F. P. Cortes, and S. Bampi, “A tool for automatic
design of analog circuits based on gm/ID methodology,” IEEE
ISCAS, 2006.

2015-12 Lecture 8 gm/ID slide 59

 References on EKV
• E. A. Vittoz and J. Felrath, “CMOS analog integrated circuits
based on weak inversion operation,” IEEE J. Solid-State
Circuits, vol. 12, no. 3, pp. 224-231, June 1977.
• E. A. Vittoz, “Low-power low-voltage limitations and prospects
in analog design,” in Proc. Workshop Advances in Analog
Circuit Design, Eindhoven, Mar. 1994.
• A good webpage on EKV by Enz:
http://www.ieee.org/portal/pages/sscs/08Summer/Enz.html

2015-12 Lecture 8 gm/ID slide 60

 Project Assignment
• Use 0.18 um (bulk or SOI) to design the OTA
presented in this lecture.
• Use HSPICE level 34 model to fit the gm/ID vs I
curve.
• Size the transistors to achieve the maximum
possible performance.
• Discuss the performance trade-offs:
– Gain, transition frequency (fT), PM, slew rate (SR)
– Power and area
– Noise

2015-12 Lecture 8 gm/ID slide 67