Question Bank DFTS
BE 4/4 ECE II Semester Elective II
Unit I
1. Distinguish between failures and faults in digital system.
2. A first generation computer contains 400 components with a failure rate of 0.08% per 40
hrs; Find the average number of failures per hour.
3. A first generation computer contain 10,000 thermionic valves each with λ=0.5%(1000Hr)
What is the period of 99% reliability
4. Derive relationship between reliability and failure rate (or) Hint: Exponential failure law
5. Write short notes on (i) Maintainability (ii) Availability (iii) MTTR
6. Derive the relationship between Reliability and MTBF
7. Explain reliability of series systems.
8. Find output F as shown in fig
9. Determine the test sets for s-a-0 and 1 fault at nodes 1 , 2, 3 and 4 ( Use fault table
method)
10. Classify stuck at fault models.
11. Classify temporary faults.
12. Explain stuck at and bridging faults in digital system with example
13. Explain path sensitization method with example and write its limitations.
14. List out properties of Boolean difference method
15. Find test vector for detecting the fault s-a-1 as shown in figure using Boolean difference
method and compare with path sensitization method
16. Explain random testing method with diagram.
17. Explain transition count testing method
18. Draw signature analyzer circuit and explain its operation
19. Explain reliability of parallel systems.
20. Find test vector for detecting the fault s-a-0 on line “a” using Boolean difference method
Unit II
21. Explain the terms (i) fault prevention (ii) fault tolerance.
22. Explain Triple modular redundancy
23. Explain Triplicate Modular Redundancy
24. Explain use of error correcting codes using fault tolerant state table.
25. Give a block diagram of hybrid redundancy scheme.
26. Explain in detail about dynamic redundancy scheme for obtaining fault tolerance
27. Describe the concept of sift out modular redundancy (SMR).
28. Write short notes on 5MR system
29. How to generate signature using PRBS.
30. What is aliasing error in transition count testing method
Unit III
31. Explain importance of software redundancy in fault tolerant systems
32. Define the terms Time redundancy and N version programming
33. Explain in detail the following practical fault tolerant systems
(a) Pluribus
(b) ESS
(c) COMTRAC
(d) Space shuttle computer system
(e) COPRA
34. Explains in detail a scheme for fault tolerant design for VLSI chips
35. Explain operation of practical fault tolerance multiprocessor.
Unit IV
36. Define fault secure and self testing.
37. Explain use of Berger codes for self checking in sequential circuits
38. Explain checker using m out of n code with example
39. What is fail safe design
40. Explain totally self checking checkers using m out of n codes
41. Explain partially self checking checkers.
42. Classify faults in PLA.
43. What is need for self checking circuits
44. List out various steps involved in the design of totally self checking checker for low cost
residue code
45. Explain totally self checking checkers for separable codes
Unit V
46. Explain the terms Controllability and Observability ( Hint :Two aspect of DFT)
47. Explain Reed-Muller expansion technique.
48. Discuss how use of control logic enhances controllability.
49. Explain in detail how three-level OR-AND-OR design is used to improve testability.
50. Explain Syndrome testable design
51. Calculate syndrome value S for the circuits shown in figures a and b
52. Draw block diagram of BIDCO.
53. Explain in detail how built in test is used to detect and isolate a faulty component is a
circuit.
54. Explain operation MISR with neat diagram
55. Explain in detail the various means employed to incorporated testability into logic
boards
---------------------------------------xxxxx------------------------------------------------
