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Logic Circuit for Generator Status Indication

The document describes a logic circuit design that indicates the number of functioning generators using colored lights. It derives the Boolean expressions for the green, amber, and red lights based on the states of three generators G1, G2, and G3. It provides the VHDL code and test bench to test the design, as well as a schematic and timing diagram. The design uses the lights such that green is on if all three generators are working, amber if two are working, and red if fewer than two.

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27 views5 pages

Logic Circuit for Generator Status Indication

The document describes a logic circuit design that indicates the number of functioning generators using colored lights. It derives the Boolean expressions for the green, amber, and red lights based on the states of three generators G1, G2, and G3. It provides the VHDL code and test bench to test the design, as well as a schematic and timing diagram. The design uses the lights such that green is on if all three generators are working, amber if two are working, and red if fewer than two.

Uploaded by

Thamidu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Name: P.T.R.

Muthukumarana Index No: 170393U

Task: The task is to build a logic circuit that will indicate the number of correctly functioning
generators. If all three generators are working, only the green light is on. If only two generators
are working only the amber light is on. If less than two generators are working only the red light
is on.

Derivation of the simplified Boolean expressions


Here G1, G2 and G3 are the three generators and 0 state imply it is not working and 1 state imply
it is working.
Green Light – LG

Truth Table Karnaugh Map


G1 G2 G3 LG
0 0 0 0 G1G2 00 01 11 10
0 0 1 0 G3
0 1 0 0 0 0 0 0 0
0 1 1 0
1 0 0 0 1 0 0 1 0
1 0 1 0
1 1 0 0
1 1 1 1

Simplified expression: LG = 𝐺1 𝐺2 𝐺3

Amber Light – LA
Truth Table Karnaugh Map
G1 G2 G3 LA
0 0 0 0 G1G2 00 01 11 10
0 0 1 0 G3
0 1 0 0 0 0 0 1 0
0 1 1 1
1 0 0 0 1 0 1 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Simplified expression: LA = 𝐺1̅ 𝐺2 𝐺3 + 𝐺1 𝐺2 𝐺̅3 + 𝐺1 𝐺̅2 𝐺3


Red Light – LR
Truth Table Karnaugh Map
G1 G2 G3 LR
0 0 0 1 G1G2 00 01 11 10
0 0 1 1 G3
0 1 0 1 0 1 1 0 1
0 1 1 0
1 0 0 1 1 1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

Simplified expression: LR =𝐺1̅ 𝐺̅3 + 𝐺̅2 𝐺̅3 + 𝐺̅2 𝐺̅3

VHDL code of the design (Without header comments)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- X - Green Light, Y - Amber Light, Z - Red Light

entity Circuit2 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
X : out STD_LOGIC;
Y : out STD_LOGIC;
Z : out STD_LOGIC);
end Circuit2;

architecture Behavioral of Circuit2 is

begin

X <= A AND B AND C;


Y <= (NOT(A) AND B AND C) OR (A AND B AND NOT(C)) OR (A AND NOT(B)
AND C);
Z <= (NOT(A) AND NOT(B)) OR (NOT(C) AND NOT(A)) OR (NOT(C) AND
NOT(B));

end Behavioral;
Schematic circuit from Vivado

Test bench code (Without header comments)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Circuit2Sim is
-- Port ( );
end Circuit2Sim;

architecture Behavioral of Circuit2Sim is

COMPONENT Circuit2
PORT( A, B, C : IN STD_LOGIC;
X, Y, Z : OUT STD_LOGIC);
END COMPONENT;

signal A, B, C : std_logic;
signal X, Y, Z : std_logic;

begin

UUT: Circuit2 PORT MAP(


A => A,
B => B,
C => C,
X => X,
Y => Y,
Z => Z
);

process
begin

-- Input: 000
A <= '0'; -- set initial values
B <= '0';
C <= '0';

WAIT FOR 100 ns; -- after 100 ns change inputs

-- Input: 001
C <= '1';

WAIT FOR 100 ns; --change again

-- Input: 010
B <= '1';
C <= '0';

WAIT FOR 100 ns; --change again

-- Input: 011
C <= '1';

WAIT FOR 100 ns; --change again

-- Input: 100
A <= '1';
B <= '0';
C <= '0';

WAIT FOR 100 ns; --change again

-- Input: 101
C <= '1';

WAIT FOR 100 ns; --change again

-- Input: 110
B <= '1';
C <= '0';
WAIT FOR 100 ns; --change again

-- Input: 111
C <= '1';

WAIT; -- will wait forever


end process;

end Behavioral;

Timing Diagram

Conclusions

 The corresponding Boolean equations for even a simple task are not much simplified.
 The simulator can be used with test bench code to test the design before programming
the device.

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