MICROPROCESSOR LAB PROJECT

EC – 316

MADE BY:-

MANISH MEENA 96/EC/13

RAHUL VASHIST 132/EC/13

FACULTY ADVISOR:-

PROF. DHANANJAY V. GADRE

 ACKNOWLEDGEMENT

We would sincerely like to thank Associate Prof. Dhananjay V. Gadre for

providing us this opportunity as a part of EC-316 coursework and for his
endless support and motivation during the entire project development.
We would also like to express our gratitude to our family, friends who
helped us throughout the project. A special thanks to Vinod Sir and
whole CEDT team, who helped us with the necessary components and
tools required for the project completion.
 TABLE OF CONTENTS

1. INTRODUCTION
2. PROJECT DESCRIPTION
i) Block Diagram
ii) Schematic
iii) Board File
iv) Basic Description
3. MEMORY INTERFACING
4. COMPONENTS REQUIRED
5. PICTURES FROM THE PROJECT
6. CODE USED
7. GANTT CHART
8. TOOLS USED
9. CONCLUSION
10. BIBLIOGRAPHY
 SYNOPSIS

Tic-tac-toe is one of the most famous and simplest games of all times. In
this game a 3X3 matrix is used to place O or X in the nine available spaces
by two competing players. In this game a player can win in eight different
ways i.e. by forming either three rows or three columns or two diagonals
using his/her given symbol (O or X).

In this project we are representing the 3X3 matrix using 9 bi-color LEDs,
where orange color represents O and green color represents X. Players
can choose a position from the initially available nine positions using a
9 push button. A LCD is also installed to show which player is won

SeT uP aNd Initialization:

1. Connect power cable and wait for system peripherals to initialize

2. System display the Tic Tac Toe on the LCD display.
3. After this player have to choose which one is player1.

WHaT NexT ?

The system automatically assign green color to player1 and red

Color to player2:
The player has to make a pattern by corresponding color.

Whichever player is make the pattern first he/she will be the

winner of the match.

The lcd display the name of the winner (i.e. player1

wins/ player2 wins)

Figure showing animated interface of game

 INTRODUCTION

The 8085 microprocessor was introduced by Intel in 1976 as a successor

to the Intel 8080 microprocessor. The 8085 is upward compatible with
its predecessor, with only 2 minor instructions added to support its
interrupt and input-output features. The 8085 is a conventional Von-
Neumann design. Since its advent, the 8085 microprocessor has found
use in numerous applications such as early personal computers as well
as in several NASA space physics missions in the 1990s.

Few of its features are:

1. The 8085 has 16 signal lines that are used as the address lines,
which are divided into two segments: the higher order
(A8 to A15) and lower order address lines (AD0 TO AD7).

2. 8 bit data bus

3. 6 general purpose 8 bit registers: B,C,D,E,H,L and Accumulator.

the 8085 is an Accumulator based microprocessor.

4. Control signals, status signals and interrupts

The 8085 is available as a 40 pin DIP IC.

Figure 1: Pin Diagram of the 8085

BLOCK DIAGRAM
Schematic
BOARD FILE
DESCRIPTION OF THE SCHEMATIC
Basic Components

 Latch: The 74HC573 is an 8 bit D type transparent latch with three

state outputs. It features a latch enable(LE) and an output
enable(OE').

Functional Diagram of the

74HC573

The 74HC573 is made up of 8 D-type flip flops with a parallel input

parallel output connection, which allows output of 8 bit simultaneously
on the data bus lines. Each flip flop is enabled when the LE is high and
the OE' is low. It is generally used for interfacing output peripherals
( LEDs, seven segment display etc.) with the microprocessor.
 Logic Gates: Logic gates are the fundamental components of
most digital circuits. Basic logic gate ICs such as AND(7408),
OR(7432) and NAND(7400) are usually employed in
schematics for microprocessor based circuits to design the
necessary addresses for the various input and output ports.
This is further explained in the topic "Decoding Logic" under
the section "Schematic Description of the Project".

 Decoders: The decoder is a logic circuit that identifies each

combination of the signalspresent at its input. In general, if a decoder
has 'n' input lines, then the number of output lines will be '2n' . Various
types of decoder circuits are available for a user; for example, 74139
(a dual 2 to 4 line decoder) and 74138( a 3 to 8 line decoder).

A functional diagram of a
2-to-4 line decoder
Power Supply: This is the most important sub-circuit which
is required to run any schematic design's implementation
on a printed circuit board. Pin number 40 of the 8085,
namely 'Vcc', requires a steady supply of 5 volts. This can be
provided either by designing a regulated power supply
(linear or switched) for the circuit or by using a USB input
port, which can be connected to laptop

p.
Decoding Logic

The very fundamental concept involved in designing the schematic

of this project is assigning suitable addresses to the various input
and output ports, as well as appropriate memory address ranges
for both RAM and ROM. The decoding circuit is generated using
basic digital circuits such as latches, buffers and logic gates. The
chip enable pin for the buffers and the latches is enabled through a
combination of their desired address and the necessary control
signal.
Input-Output Interfacing"
Decoding logic for input output interfacing is implemented using 3 to 8
decoder(74138),Address line A2 A3 A4 is used as the three select lines
where as A5 A6 A7 is used as enabling of the decoder,
A0 & A1 are directly connected to the A0 & A1 of the both 8255

Table1: Port Addresses

Ports A7 A6 A5 A4 A3 A2 A1 A0 Hex Address

PORT1/A 1 0 0 0 0 0 0 0 80H
PORT1/B 1 0 0 0 0 0 0 1 81H
PORT1/C 1 0 0 0 0 0 1 0 82H
PORT1/CONTROL REGISTER 1 0 0 0 0 0 1 1 83H
PORT2/A 1 0 0 0 0 1 0 0 84H
PORT2/B 1 0 0 0 0 1 0 1 85H
PORT2/C 1 0 0 0 0 1 1 0 86H
PORT2/CONTROL REGISTER 1 0 0 0 0 1 1 1 87H

Here we have done absolute decoding of input output port, we have

eight fixed address to access I/O ports, we can also do partial decoding
for I/O port where we have multiple address for a single port, which is
not good if we have more no. of port
 MEMORY INTERFACING

Memory interfacing refers to the interfacing of RAM and

EEPROM with the 8085 by allocating appropriate address ranges
to both. The RAM used is 58C256, which is a 32kB static ram and
is available in a 28 pin DIP package. Static rams are made up of
flip-flops and they store the bits as voltages. EEPROM used is
AT28c256, which is available as a 28 pin DIP package.

The lower order address bus of the 8085 microprocessor is

multiplexed with the 8 bit data bus. The buses are de-multiplexed
using a 74HC573 Address Latch, which is enabled using the A15
address line from the microprocessor. When the latch is enabled,
i.e. A15 =1, the RAM is selected and otherwise the ROM is selected.
The remaining 15 address lines are used for both RAM and ROM,
thus giving a size of 32kB for each.

The memory address map for the RAM and ROM are:

ROM: 0000H to 7FFFH

RAM: 8000H to FFFF

Read write logic

read and write logic for memory as well as input/output chips is

implemented using 3 to 8 decoder, three select lines for decoder are
WR*, RD* & IO/M* from 8085, IO/M* is used to select whether it is
memory or I/O and RD* & WR* are used to select whether it is read or
write command, by use of these three lines we can make all read and
write signal for memory and i/o chip.

OPERATION IO/M* RD* WR*

MEMORY READ (Y1) 0 0 1
MEMORY WRITE (Y2) 0 1 0
I/O READ (Y5) 1 0 1
I/O WRITE (Y6) 1 1 0
 COMPONENTS REQUIRED

Quantity DEVICE PACKAGE PARTS DESCRIPTION

2 10-XX B3F-10XX RESET, OMRON SWITCH

SWITCH
9 10-XX B3F-10XX S1, S2, S3, OMRON SWITCH
S4, S5, S6,
S7, S8, S9
1 16X2LCD 16X2LCD LCD

1 58C256P DIL28-6 ROM-58C256 MEMORY

1 62256P DIL28-6 RAM-62256P MEMORY

1 8085 DIL40 8085 MICROPROCESSOR

2 82C55A DIL40 PORTS- PPI

82C55A,
PORTS-
82C55A1
13 C-EU025-024X044 C025-024X044 C1, C2, C3, CAPACITOR
C5, C7, C8,
C9, C10, C12,
C14, C15,
C16, C17
1 C-EU050-024X044 C050-024X044 C6 CAPACITOR(EU)

2 C2,5-3 C2.5-3 C11, C18 CAPACITOR

2 CPOL-EUE5-8.5 E5-8,5 C4, C13 POLAR CAPACITOR

1 CRYSTALHC49US HC49US Q2 CRYSTAL

1 LED3MM LED3MM LED@SOD LED

29 R-EU_0204/7 0204/7 R1, R2, R3, RESISTOR

R4, R5, R6,
R7, R8, R9,
R10, R11,
R12, R13,
R14, R15,
R16, R17, R18
1 74HCT04N DIL14 NOT NOT GATE

2 74HCT138N DIL16 DECODER, 3 TO 8 DECODER

DECODER1
1 74HCT573N DIL20 ADDLATCH LATCH

1 LED5MM LED5MM LED1 LED

1 PRESET_LR PRESET_LR PRESET

9 TLUV5300 TLUV5300 LED2, LED3, BI-COLOR LED

LED4, LED5,
 LED6, LED7,
LED8, LED9,
LED10
3 UDN2981A DIL18 IC1, IC2, IC3 DRIVER

1 USBSMD USB-MINIB USB USB PORT

PICTURES FROM THE PROJECT
 CODE USED

.ORG 0000H

LXI SP, 0000H ;STACK POINTER INITIALISATION

MVI A, 10010000B ;8255 INITIALISATION

OUT 087H

INIT: MVI A, 00110000B

MOV B, A

CALL OUTPUT

CALL CMDOUT

CALL CMDOUT

MVI A, 00111000B ;8 BIT, 2 LINES, 5X8 DISP

CALL CMDOUT

MVI A, 00001000B ;DISPLAY OFF

CALL CMDOUT

MVI A, 00000001B ;CLEAR DISPLAY

CALL CMDOUT

MVI A, 00000110B ;ENTRY MODE SET, SHIFT AND INCREMENT CURSOR

CALL CMDOUT

MVI A, 00001100B ;DISPLAY ON CURSOR, BLINKING OFF

CALL CMDOUT

DISP1: MVI A, 80H ;START POSITION

CALL CMDOUT

MVI A,20H

CALL DTAOUT

MVI A, 81H ;START POSITION

CALL CMDOUT

MVI A,20H

CALL DTAOUT

MVI A, 82H ;START POSITION

CALL CMDOUT

MVI A,54H

CALL DTAOUT
MVI A, 83H ;START POSITION

CALL CMDOUT

MVI A,49H

CALL DTAOUT

MVI A, 84H ;START POSITION

CALL CMDOUT

MVI A,43H

CALL DTAOUT

MVI A, 85H ;START POSITION

CALL CMDOUT

MVI A,20H

CALL DTAOUT

MVI A, 86H ;START POSITION

CALL CMDOUT

MVI A,54H

CALL DTAOUT

MVI A, 87H ;START POSITION

CALL CMDOUT

MVI A,41H

CALL DTAOUT

MVI A, 88H ;START POSITION

CALL CMDOUT

MVI A,43H

CALL DTAOUT

MVI A, 89H ;START POSITION

CALL CMDOUT

MVI A,20H

CALL DTAOUT

MVI A, 8AH ;START POSITION

CALL CMDOUT

MVI A,54H

CALL DTAOUT

MVI A, 8BH ;START POSITION

CALL CMDOUT

MVI A,4FH
 CALL DTAOUT

MVI A, 8CH ;START POSITION

CALL CMDOUT

MVI A,45H

CALL DTAOUT

MVI A, 8DH ;START POSITION

CALL CMDOUT

MVI A,45H

CALL DTAOUT

NOP

NOP

NOP

NOP

NOP

MVI A,00H

STA 8050H

STA 8060H

MVI A,04H

STA 9001H

MVI A,05H

STA 9002H

MVI A,06H

STA 9003H

MVI A,07H

STA 9004H

MVI A,08H

STA 9005H

MVI A,09H

STA 9006H

MVI A,0AH

STA 9007H

MVI A,0BH

STA 9008H

MVI A,0CH

STA 9009H
 MVI A,98H

OUT 87H

MVI A,80H

OUT 83H

MVI A,00H

MVI B,00H

PLAYER1:
IN 84H

ANI 0FFH

CPI 0FFH

JZ PLAYER1

CALL DEBOUNCE1

PLAYER2:
IN 84H

ANI 0FFH

CPI 0FFH

JZ PLAYER2

CALL DEBOUNCE2

KEYPUSH1: IN 84H

ANI 0FFH

CPI 0FFH

JNZ LEDGLOW1

JMP PLAYER1

KEYPUSH2: IN 84H

ANI 0FFH

CPI 0FFH

JNZ LEDGLOW2

JMP PLAYER2

LEDGLOW1: MOV B,A

CPI 0FEH
 JZ GREEN1

JMP GREEN2

LEDGLOW2: MOV B,A

CPI 0FEH

JZ RED1

JMP RED2

RED1:

MVI A,02H

STA 8050H

OUT 80H

MVI A,00H

STA 9001H

CALL PTCHECKER

JMP PLAYER1

GREEN1:

MVI A,01H

STA 8050H

OUT 80H

MVI A,01H

STA 9001H

CALL PTCHECKER

JMP PLAYER2

GREEN2:
MOV A,B

CPI 0FDH

JNZ GREEN3

MVI A,04H

STA 8051H

OUT 80H

MVI A,01H
 STA 9002H

CALL PTCHECKER

JMP PLAYER2

RED2:

MOV A,B

CPI 0FDH

JNZ RED3

MVI A,08H

STA 8051H

OUT 80H

MVI A,00H

STA 9002H

CALL PTCHECKER

JMP PLAYER1

GREEN3:
MOV A,B

CPI 0FBH

JNZ GREEN4

MVI A,10H

STA 8052H

OUT 80H

MVI A,01H

STA 9003H

CALL PTCHECKER

JMP PLAYER2

RED3:

MOV A,B

CPI 0FBH

JNZ RED4
 MVI A,20H

STA 8052H

OUT 80H

MVI A,00H

STA 9003H

CALL PTCHECKER

JMP PLAYER1

GREEN4:
MOV A,B

CPI 0F7H

JNZ GREEN5

MVI A,40H

STA 8053H

OUT 80H

MVI A,01H

STA 9004H

CALL PTCHECKER

JMP PLAYER2

RED4:

MOV A,B

CPI 0F7H

JNZ RED5

MVI A,80H

STA 8053H

OUT 80H

MVI A,00H

STA 9004H

CALL PTCHECKER

JMP PLAYER1

GREEN5:
MOV A,B
 CPI 0EFH

JNZ GREEN6

MVI A,01H

STA 8054H

OUT 81H

MVI A,01H

STA 9005H

CALL PTCHECKER

JMP PLAYER2

RED5:

MOV A,B

CPI 0EFH

JNZ RED6

MVI A,02H

STA 8054H

OUT 81H

MVI A,00H

STA 9005H

CALL PTCHECKER

JMP PLAYER1

GREEN6:
MOV A,B

CPI 0DFH

JNZ GREEN7

MVI A,04H

OUT 81H

STA 8055H

MVI A,01H

STA 9006H

CALL PTCHECKER
 JMP PLAYER2

RED6:

MOV A,B

CPI 0DFH

JNZ RED7

MVI A,08H

OUT 81H

STA 8055H

MVI A,00H

STA 9006H

CALL PTCHECKER

JMP PLAYER1

GREEN7:
MOV A,B

CPI 0BFH

JNZ GREEN8

MVI A,10H

OUT 81H

STA 8056H

MVI A,01H

STA 9007H

CALL PTCHECKER

JMP PLAYER2

RED7:

MOV A,B

CPI 0BFH

JNZ RED8

MVI A,20H

OUT 81H
 STA 8056H

MVI A,00H

STA 9007H

CALL PTCHECKER

JMP PLAYER1

GREEN8:
;CPI 7FH

;JNZ GREEN9

MVI A,40H

OUT 81H

STA 8057H

MVI A,01H

STA 9008H

CALL PTCHECKER

JMP PLAYER2

RED8:

;CPI 7FH

;JNZ RED9

MVI A,80H

OUT 81H

STA 8057H

MVI A,00H

STA 9008H

CALL PTCHECKER

JMP PLAYER1

PTCHECKER:
MVI A,00H

LXI H,8050H

ORA M

INX H

ORA M
 INX H

ORA M

INX H

ORA M

OUT 80H

MVI A,00H

LXI H,8054H

ORA M

INX H

ORA M

INX H

ORA M

INX H

ORA M

OUT 81H

LDA 9001H

LXI H,9002H

CMP M

JNZ PT2

INX H

CMP M

JZ PTFOUND

PT2:

LDA 9004H

LXI H,9005H

CMP M

JNZ PT3

INX H

CMP M

JZ PTFOUND

PT3:

LDA 9007H

LXI H,9008H

CMP M
 JNZ PT4

INX H

CMP M

JZ PTFOUND

PT4:

LDA 9001H

LXI H,9004H

CMP M

JNZ PT5

LXI H,9007H

CMP M

JZ PTFOUND

PT5:

LDA 9002H

LXI H,9005H

CMP M

JNZ PT6

LXI H,9008H

CMP M

JZ PTFOUND

PT6:

LDA 9003H

LXI H,9006H

CMP M

JNZ PT7

LXI H,9009H

CMP M

JZ PTFOUND

PT7:

LDA 9001H

LXI H,9005H

CMP M

JNZ PT8

LXI H,9009H
 CMP M

JZ PTFOUND

PT8:

LDA 9003H

LXI H,9005H

CMP M

JNZ NPFOUND

LXI H,9007H

CMP M

JZ PTFOUND

NPFOUND:
RET

MVI A, 80H ;START POSITION

CALL CMDOUT

MVI A,20H

CALL DTAOUT

PTFOUND:
CPI 01H

JNZ PF2

MVI A, 80H ;START POSITION

CALL CMDOUT

MVI A,50H

CALL DTAOUT

MVI A, 81H ;START POSITION

CALL CMDOUT

MVI A,4CH

CALL DTAOUT

MVI A, 82H ;START POSITION

CALL CMDOUT

MVI A,41H

CALL DTAOUT

MVI A, 83H ;START POSITION

CALL CMDOUT

MVI A,59H

CALL DTAOUT
MVI A, 84H ;START POSITION

CALL CMDOUT

MVI A,45H

CALL DTAOUT

MVI A, 85H ;START POSITION

CALL CMDOUT

MVI A,52H

CALL DTAOUT

MVI A, 86H ;START POSITION

CALL CMDOUT

MVI A,31H

CALL DTAOUT

MVI A, 87H ;START POSITION

CALL CMDOUT

MVI A,20H

CALL DTAOUT

MVI A, 88H ;START POSITION

CALL CMDOUT

MVI A,57H

CALL DTAOUT

MVI A, 89H ;START POSITION

CALL CMDOUT

MVI A,49H

CALL DTAOUT

MVI A, 8AH ;START POSITION

CALL CMDOUT

MVI A,4EH

CALL DTAOUT

MVI A, 8BH ;START POSITION

CALL CMDOUT

MVI A,53H

CALL DTAOUT

MVI A, 8CH ;START POSITION

CALL CMDOUT

MVI A,20H
 CALL DTAOUT

MVI A, 8DH ;START POSITION

CALL CMDOUT

MVI A,20H

CALL DTAOUT

MVI A, 8EH ;START POSITION

CALL CMDOUT

MVI A,20H

CALL DTAOUT

HLT

PF2:

;CPI 00H

;JNZ PNF

MVI A, 80H ;START POSITION

CALL CMDOUT

MVI A,50H

CALL DTAOUT

MVI A, 81H ;START POSITION

CALL CMDOUT

MVI A,4CH

CALL DTAOUT

MVI A, 82H ;START POSITION

CALL CMDOUT

MVI A,41H

CALL DTAOUT

MVI A, 83H ;START POSITION

CALL CMDOUT

MVI A,59H

CALL DTAOUT

MVI A, 84H ;START POSITION

CALL CMDOUT

MVI A,45H

CALL DTAOUT

MVI A, 85H ;START POSITION

CALL CMDOUT
 MVI A,52H

CALL DTAOUT

MVI A, 86H ;START POSITION

CALL CMDOUT

MVI A,32H

CALL DTAOUT

MVI A, 87H ;START POSITION

CALL CMDOUT

MVI A,20H

CALL DTAOUT

MVI A, 88H ;START POSITION

CALL CMDOUT

MVI A,57H

CALL DTAOUT

MVI A, 89H ;START POSITION

CALL CMDOUT

MVI A,49H

CALL DTAOUT

MVI A, 8AH ;START POSITION

CALL CMDOUT

MVI A,4EH

CALL DTAOUT

MVI A, 8BH ;START POSITION

CALL CMDOUT

MVI A,53H

CALL DTAOUT

MVI A, 8CH ;START POSITION

CALL CMDOUT

MVI A,20H

CALL DTAOUT

MVI A, 8DH ;START POSITION

CALL CMDOUT

MVI A,20H

CALL DTAOUT

MVI A, 8EH ;START POSITION

 CALL CMDOUT

MVI A,20H

CALL DTAOUT

HLT

DEBOUNCE1: PUSH B

PUSH PSW

LXI B, 041CH ;5MS

LOOP1: DCX B

MOV A,C

ORA B

JNZ LOOP1

POP PSW

POP B

CALL KEYPUSH1

DEBOUNCE2: PUSH B

PUSH PSW

LXI B, 041CH ;5MS

LOOP2: DCX B

MOV A,C

ORA B

JNZ LOOP2

POP PSW

POP B

CALL KEYPUSH2

CMDOUT: MOV B,A ;SAVE

CALL CHK

OUTPUT: MVI A, 01000000B;RS=0,RW=0,EN=1

 OUT 086H

RET

DTAOUT: MOV B, A ;SAVE DATA BYTE

CALL CHK

MVI A, 01010000B;RW=0,RS=1,E=1

OUT 086H

MOV A, B;RESTORE

OUT 085H

RET

CHK: MVI A, 10010010B;SET B AS INPUT PORT

OUT 87H

READ: MVI A,01100000B;RS=0,RW=1,EN=1;ENABLE HIGH

OUT 086H

IN 085H;CHECK D7

RLC;CARRY

MVI A, 10100000B;RS=0,RW=1,EN=LOW

OUT 85H

JC READ ;LOOP TILL BUSY

MVI A,10000001B;RS=0,RW=0,EN=HIGH

MVI A, 10010000B ;SET B AS OUTPUT

OUT 87H

MOV A,B

OUT 85H

RET

.END

GANTT CHART
 COMPARISON WITH ACTUAL RESULT

STEP EXPECTED DURATION ACTUAL DURATION

PROPOSAL OF PROJECT 5-11 JAN 2016 5-11 JAN 2016

LEARNING 8085 ARCHITECTURE 10 JAN-09 FEB 2016 10 JAN-9 FEB 2016
BLOCK DIAGRAM/FLOW CHART 07FEB-18 FEB 2016 07 JAN-18 FEB 2016
RAM ROM INTERFACING 14 FEB-25 FEB 2016 14 FEB-1 MARCH 2016
LED AND KEYBOARD
INTERFACING 17 FEB-2 MARCH 2016 17 FEB-5 MARCH 2016
LCD INTERFACING 21 FEB-4 MARCH 2016 21 FEB-15 MARCH 2016
FINAL SCHEMATIC 23 FEB - 15 MARCH 2016 5 MARCH -30 MARCH
PROGRAMMING 1 MARCH -25 MARCH 2016 30MARCH - 25APRIL 2016
PCB FABRICATION 12 MARCH - 25 MARCH 2016 12 APRIL - 22 APRIL 2016
ASSEMBLY & TESTING 18 MARCH- 10 APRIL 2016 25 APRIL - 31 MAY 2016

STEP EXPECTED DURATION ACTUAL DURATION

PROPOSAL OF PROJECT 5-11 JAN 2016 5-11 JAN 2016

LEARNING 8085 ARCHITECTURE 10 JAN-09 FEB 2016 10 JAN-9 FEB 2016
BLOCK DIAGRAM/FLOW CHART 07FEB-18 FEB 2016 07 JAN-18 FEB 2016
RAM ROM INTERFACING 14 FEB-25 FEB 2016 14 FEB-1 MARCH 2016
LED AND KEYBOARD
INTERFACING 17 FEB-2 MARCH 2016 17 FEB-5 MARCH 2016
LCD INTERFACING 21 FEB-4 MARCH 2016 21 FEB-15 MARCH 2016
FINAL SCHEMATIC 23 FEB - 15 MARCH 2016 5 MARCH -30 MARCH
PROGRAMMING 1 MARCH -25 MARCH 2016 30MARCH - 25APRIL 2016
PCB FABRICATION 12 MARCH - 25 MARCH 2016 12 APRIL - 22 APRIL 2016
ASSEMBLY & TESTING 18 MARCH- 10 APRIL 2016 25 APRIL - 31 MAY 2016
 Tools used

Software Tools:

EAGLE 7.3.0 – for schematic and board layout

8085 Simulator IDE by OshonSoft

EEPROM programmer software.

Proteus.

Hardware Tools:
Soldering Iron
Solder

Multimeter

+5V DC Power Supply

EEPROM Programmer.

Cutter, Tweezers, Hand Files,

 CONCLUSION

We concluded that there is no bar in thinking a great project and

implementing it successfully given we have proper guidance and proper
facilities.
 BIBLIOGRAPHY

“Microprocessor Architecture, Programming, and Applications

with 8085” 5th edition

Author: Ramesh S. Gaonkar

Publisher: Penram International Publishing (India) Pvt. Ltd.

ISBN: 81-87972-09-2