Freescale Semiconductor Document Number: MC33290

Technical Data Rev 8.0, 8/2008

ISO K Line Serial Link Interface

The 33290 is a serial link bus interface device designed to provide
33290
bi-directional half-duplex communication interfacing in automotive
diagnostic applications. It is designed to interface between the
vehicle’s on-board microcontroller and systems off-board the vehicle
via the special ISO K line. The 33290 is designed to meet the ISO9141 PHYSICAL INTERFACE
Diagnostic Systems ISO9141 specification. The device’s K line bus
driver’s output is fully protected against bus shorts and
overtemperature conditions.
The 33290 derives its robustness to temperature and voltage
extremes by being built on a SMARTMOS process, incorporating
CMOS logic, bipolar/MOS analog circuitry, and DMOS power FETs.
Although the 33290 was principally designed for automotive
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applications, it is suited for other serial communication applications. D SUFFIX
It is parametrically specified over an ambient temperature range of EF SUFFIX (PB-FREE)
-40ºC ≤ TA ≤ 125ºC and 8.0 V ≤ VBB ≤ 18 V supply. The economical 98ASB42564B
SO-8 surface-mount plastic package makes the 33290 very cost 8-PIN SOICN
effective.
ORDERING INFORMATION
Features
Temperature
• Operates Over Wide Supply Voltage of 8.0 to 18V Device Package
Range (TA)
• Operating Temperature of -40 to 125°C
MC33290D/R2
• Interfaces Directly to Standard CMOS Microprocessors -40 to 125°C 8-SOICN
• ISO K Line Pin Protected Against Shorts to Ground MCZ33290EF/R2
• Thermal Shutdown with Hysteresis
• ISO K Line Pin Capable of High Currents
• ISO K Line Can Be Driven with up to 10 nF of Parasitic
Capacitance
• 8.0 kV ESD Protection Attainable with Few Additional Components
• Standby Mode: No VBat Current Drain with VDD at 5.0 V
• Low Current Drain During Operation with VDD at 5.0 V
• Pb-Free Packaging Designated by Suffix Code EF

+VBAT

VDD

33290
VDD VDD VBB
MCU
ISO K-Line
Dx CEN ISO
SCIRx D RX
T xD
SCITx D TX
GND R xD

Figure 1. 33290 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as
may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006-2008. All rights reserved.
 INTERNAL BLOCK DIAGRAM

INTERNAL BLOCK DIAGRAM

VBB 3.0 kΩ

1 50 V 20 V

200 Ω RX

6
10 V 10 V
ISO

4
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RHys
Master
Bias
CEN

8 40 V
VDD 125 kΩ
Thermal
Shutdown GND
7
125 kΩ 3
TX 2.0 kΩ
5 10 V 10 V

Figure 2. 33290 Simplified Block Diagram

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2 Freescale Semiconductor
 PIN CONNECTIONS

PIN CONNECTIONS

VBB 11 88 CEN
NC 22 77 VDD
GND 33 66 RX
ISO 44 55 TX

Figure 3. 33290 Pin Connections

Table 1. 33290 Pin Definitions

Pin Number Pin Name Definition
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1 VBB Battery power through external resistor and diode.

2 NC Not to be connected. (1)

3 GND Common signal and power return.

4 ISO Bus connection.

5 TX Logic level input for data to be transmitted on the bus.

6 RX Logic output of data received on the bus.

7 VDD Logic power source input.

8 CEN Chip enable. Logic “1” for active state. Logic “0” for sleep state.

Notes
1. NC pins should not have any connections made to them. NC pins are not guaranteed to be open circuits.

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 ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating Symbol Value Unit

VDD DC Supply Voltage VDD -0.3 to 7.0 V

VBB Load Dump Peak Voltage VBB(LD) 45 V
(2)
ISO Pin Load Dump Peak Voltage VISO 40 V
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ISO Short Circuit Current Limit IISO(LIM) 1.0 A
(3)
ESD Voltage V
Human Body Model (4) VESD1 ±2000
Machine Model (4) VESD2 ±200

ISO Clamp Energy (5) Eclamp 10 mJ

Storage Temperature Tstg -55 to +150 °C
Operating Case Temperature TC -40 to +125 °C
Operating Junction Temperature TJ -40 to +150 °C
Power Dissipation PD W
TA = 25°C 0.8
(6) (7) °C
Peak Package Reflow Temperature During Reflow , TPPRT Note 7.
Thermal Resistance RθJA °C/W
Junction-to-Ambient 150
Notes
2. Device will survive double battery jump start conditions in typical applications for 10 minutes duration, but is not guaranteed to remain
within specified parametric limits during this duration.
3. ESD data available upon request.
4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
5. Nonrepetitive clamping capability at 25°C.
6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to [Link], search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.

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 ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise
noted.
Characteristic Symbol Min Typ Max Unit

POWER AND CONTROL

VDD Sleep State Current IDD(SS) mA

Tx = 0.8 VDD, CEN = 0.3 VDD – – 0.1

VDD Quiescent Operating Current IDD(Q) mA

Tx = 0.2 VDD, CEN = 0.7 VDD – – 1.0
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VBB Sleep State Current IBB(SS) µA
VBB = 16 V, Tx = 0.8 VDD, CEN = 0.3 VDD – – 50

VBB Quiescent Operating Current IBB(Q) mA

TX = 0.2 VDD, CEN = 0.7 VDD – – 1.0

Chip Enable V
Input High-Voltage Threshold (8) VIH(CEN) 0.7 VDD – –
Input Low-Voltage Threshold (9) VIL(CEN) – – 0.3 VDD

Chip Enable Pull-Down Current (10) IPD(CEN) 2.0 – 40 µA

TX Input Low-Voltage Threshold VIL(Tx) V

RISO = 510 Ω (11) – – 0.3 x VDD

TX Input High-Voltage Threshold VIH(Tx) V

RISO = 510 Ω (12) 0.7 x VDD – –

TX Pull-Up Current (13) IPU(Tx) -40 – -2.0 µA

RX Output Low-Voltage Threshold VOL(Rx) V

RISO = 510 Ω, TX = 0.2 VDD, Rx Sinking 1.0 mA – – 0.2 VDD

RX Output High-Voltage Threshold VOH(Rx) V

RISO = 510 Ω, TX = 0.8 VDD, RX Sourcing 250 µA 0.8 VDD – –

Thermal Shutdown (14) TLIM 150 170 – °C

Notes
8. When IBB transitions to >100 µA.
9. When IBB transitions to <100 µA.
10. Enable pin has an internal current pull-down. Pull-down current is measured with CEN pin at 0.3 VDD.
11. Measured by ramping TX down from 0.7 VDD and noting TX value at which ISO falls below 0.2 VBB.
12. Measured by ramping TX up from 0.3 VDD and noting the value at which ISO rises above 0.9 VBB.
13. Tx pin has internal current pull-up. Pull-up current is measured with TX pin at 0.7 VDD.
14. Thermal Shutdown performance (TLIM) is guaranteed by design but not production tested.

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 ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (Continued)

Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise
noted.
Characteristic Symbol Min Typ Max Unit

ISO I/O

Input Low Voltage Threshold VIL(ISO) V

RISO = 0 Ω, TX = 0.8 VDD (15) – – 0.4 x VBB

Input High Voltage Threshold VIH(ISO) V

RISO = 0 Ω, TX = 0.8 VDD (16) 0.7 x VBB – –

Input Hysteresis (17) VHys(ISO) 0.05 x VBB – 0.1 x VBB V

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Internal Pull-Up Current IPU(ISO) µA
RISO = ∞ Ω, TX = 0.8 VDD, VISO = 9.0 V, VBB = 18 V -5.0 – -140

Short Circuit Current Limit (18) ISC(ISO) mA

RISO = 0 Ω, TX = 0.4 VDD, VISO = VBB 50 – 1000

Output Low Voltage VOL(ISO) V

RISO = 510 Ω, TX = 0.2 VDD – – 0.1 x VBB

Output High Voltage VOH(ISO) V

RISO = ∞ Ω, TX = 0.8 VDD 0.95 x VBB – –

Notes
15. ISO ramped from 0.8 VBB to 0.4 VBB, Monitor RX, Value of ISO voltage at which RX transitions to 0.3 VDD.
16. ISO ramped from 0.4 VBB to 0.8 VBB, Monitor RX, Value of ISO voltage at which RX transitions to 0.7 VDD.
17. Input Hysteresis, VHys(ISO) = VIH(ISO) - VIL(ISO).
18. ISO has internal current limiting.

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 ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise
noted.
Characteristic Symbol Min Typ Max Unit

Fall Time (19) tfall(ISO) µs

RISO = 510 Ω to VBB, CISO = 10 nF to Ground – – 2.0

ISO Propagation Delay (20) tPD(ISO) µs

– – 2.0
High to Low: RISO = 510 Ω, CISO = 500 pF (21)
– – 2.0
Low to High: RISO = 510 Ω, CISO = 500 pF (22)
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Notes
19. Time required ISO voltage to transition from 0.8 VBB to 0.2 VBB.
20. Changes in the value of CISO affect the rise and fall time but have minimal effect on Propagation Delay.
21. Step TX voltage from 0.2 VDD to 0.8 VDD. Time measured from VIH(ISO) until VISO reaches 0.3 VBB.
22. Step TX voltage from 0.8 VDD to 0.2 VDD. Time measured from VIL(ISO) until VISO reaches 0.7 VBB.

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 ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES

ELECTRICAL PERFORMANCE CURVES

VIL and VIH, INPUT THRESHOLD (RA-

1.2
0.6

VOL and VOH, ISO OUTPUT (RATIO)

VOH
VIH; VDD = 5.25 V, VBB = 1.0
0.575 18 V
VIH; VDD = 4.75 V, VBB =
0.8
8.0 V
0.55
VDD = 4.75 V, VBB = 8.0 V
0.6
and
0.525 VDD = 5.25 V, VBB = 18 V
0.4
VIL; VDD = 5.25 V, VBB =
0.5 18 V
0.2
VIL; VDD = 4.75 V, VBB =
VOL
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0.475 8.0 V
-50 0 50 100 150 0
-50 0 50 100 150
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)

Figure 4. ISO Input Threshold/VBB vs. Temperature Figure 6. ISO Fall Time vs. Temperature

0.95 0.7
tPD(ISO), PROPAGATION DELAY (µs)
VDD = 5.25 V, VBB = 18 V
tfall(ISO), ISO FALL TIME (µs)

0.9 PdH-L
VDD = 5.25 V, VBB = 18 V 0.6
VDD = 4.75 V, VBB = 8.0 V
0.85
0.5
0.8
0.4
0.75
VDD = 4.75 V, VBB = 8.0 V
0.3
0.7 VDD = 5.25 V, VBB = 18 V PdL-H
VDD = 4.75 V, VBB = 8.0 V
0.65 0.2
-50 0 50 100 150 -50 0 50 100 150
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 5. ISO Output/VBB vs. Temperature Figure 7. ISO Propagation Delay vs. Temperature

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 TYPICAL APPLICATIONS
INTRODUCTION

TYPICAL APPLICATIONS

INTRODUCTION

The 33290 is a serial link bus interface device conforming microcontroller to the communication bus. The 33290
to the ISO 9141 physical bus specification. The device was incorporates circuitry to interface the digital translations from
designed for automotive environment usage compliant with 5.0 V microcontroller logic levels to battery level logic and
On-Board Diagnostic (OBD) requirements set forth by the from battery level logic to 5.0 V logic levels. The 33290 is built
California Air Resources Board (CARB) using the ISO K line. using Freescale Semiconductor’s SMARTMOS process and
The device does not incorporate an ISO L line. It provides bi- is packaged in an 8-pin plastic SOIC.
directional half-duplex communications interfacing from a

FUNCTIONAL DESCRIPTION
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The 33290 transforms 5.0 V microcontroller logic signals passive pull-up to VDD, while the CEN input has an internal
to battery level logic signals and visa versa. The maximum passive pull-down to ground.
data rate is set by the fall time and the rise time. The fall time A pull-up to battery is internally provided as well as an
is set by the output driver. The rise time is set by the bus active data pull-down. The internal active pull-down is
capacitance and the pull-up resistors on the bus. The fall time current-limit-protected against shorts to battery and further
of the 33290 allows data rates up to 150 kbps using a 30 protected by thermal shutdown. Typical applications have
percent maximum bit time transition value. The serial link reverse battery protection by the incorporation of an external
interface will remain fully functional over a battery voltage 510 Ω pull-up resistor and diode to battery.
range of 6.0 to 18 V. The device is parametrically specified
Reverse battery protection of the device is provided by
over a dynamic VBB voltage range of 8.0 to 18 V.
using a reverse battery blocking diode (“D” in the Simplified
Required input levels from the microcontroller are ratio- Application Diagram on page 1). Battery line transient
metric with the VDD voltage normally used to power the protection of the device is provided for by using a 45 V zener
microcontroller. This enhances the 33290’s ability to remain and a 500 Ω resistor connected to the VBB source as shown
in harmony with the RX and TX control input signals of the in the same diagram. Device ESD protection from the
microcontroller. The RX and TX control inputs are compatible communication lines exiting the module is through the use of
with standard 5.0 V CMOS circuitry. For fault-tolerant the capacitor connected to the VBB device pin and the
purposes the TX input from the microcontroller has an internal capacitor used in conjunction with the 27 V zener connected
to the ISO pin.

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Freescale Semiconductor 9
 PACKAGING
PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit [Link] and perform a keyword search using the “98A” listed below.
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ARCHIVE INFORMATION

D SUFFIX
EF SUFFIX (PB-FREE)
8-PIN
PLASTIC PACKAGE
98ASB42564B
REV. U

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 REVISION HISTORY

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES

6.0 7/2006 • Implemented Revision History page

• Converted to Freescale format and updated to the prevailing for and style
• Added Pb-free suffix EF
• Removed MC33290EG/R2 and replaced with MCZ33290EG/R2 in the Ordering
Information block
7.0 10/2006 • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter
from Maximum Ratings on page 4. Added note with instructions to obtain this information
from [Link].
8.0 8/2008 • Corrected the Document header information.
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• Updated to the current Freescale form and style.

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Freescale Semiconductor 11
ARCHIVE INFORMATION

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MC33290
Rev 8.0
8/2008