Unit 2: 8051 Instruction set

Addressing Modes:
The CPU can access data in various ways. The data could be in a register, or in
memory, or be provided as an immediate value. These various ways of accessing data are
called addressing modes.
The 8051 have 5 different addressing modes. They are as follows:
1. immediate
2. register
3. direct
4. register indirect
5. indexed

1) Immediate addressing mode:

In this addressing mode data is immediately available & the operand comes
immediately after the opcode.In between operand and opcode pound sign, “#” is used.
This addressing mode can be used to load information into any of the registers, including
the DPTR register.
e.g.:

2) Register addressing mode:

In this addressing mode data is in register & it can be moved to other register. “,”
sign is used between registers.
e.g.

Movement of data between registers (banks) is not allowed. For example, the instruction
“MOV R4, R7″ is invalid.
In these two addressing modes, the operands (data) are either inside the registers or
immediately available. But when data is available in memory (RAM/ROM) then other
modes are used these are:
3) Direct addressing mode:
There are 128 bytes of RAM in the 8051. It is divided as 00 to 1FH for register
banks and stack. 20-2F for bit addressable RAMS & 30-7F is used for scratch pad. The
register bank locations are accessed by the register names of R0 – R7, but data in location
30-7F is accessed by giving address.
In the direct addressing mode, the data is in a RAM memory location whose
address is known, and this address is given as a part of the instruction.

In this mode we can give address of register instead of name.

Stack and direct addressing mode

Another major use of direct addressing mode is the stack. In the 8051 family, only
direct addressing mode is allowed for pushing onto the stack.
Therefore, an instruction such as “PUSH A” is invalid. Pushing the accumulator
onto the stack must be coded as “PUSH 0E0H” where OEOH is the address of register A.
Similarly, pushing R3 of bank 0 is coded as “PUSH 03″.
Direct addressing mode must be used for the POP instruction as well. For
example, “POP 04″ will pop the top of the stack into R4 of bank 0.
Looping is not possible in direct addressing mode.
4) Register indirect addressing mode:
In the register indirect addressing mode, data is at memory location & address of
this memory location is stored in registers R0 and R1 only. They must be preceded by the
“@” sign, as shown below.

Advantage of register indirect addressing mode

One of the advantages of register indirect addressing mode is that it makes
accessing data dynamic rather than static as in the case of direct addressing mode.
Example:
Indexed addressing mode:
Indexed addressing mode is widely used in accessing data elements of look-up
table entries located in the program ROM space. The instruction used for this purpose is
“MOVC A, @A+DPTR”. The 16-bit register DPTR and register A are used to form the
address of the data element stored in on-chip ROM. The “C” means code.
Instruction Set:
Arithmetic Instruction:
Addition:

The instruction ADD is used to add two operands. The destination operand is
always in register A while the source operand can be a register, immediate data, or in
memory. The memory-to-memory arithmetic operations are never allowed in 8051
Assembly language.

Example:
Show how the flag register is affected by the
following instructions.
After the addition, register A (destination)
contains 00 and the flags are as follows:
CY = 1 since there is a carry out from D7.
P = 0 because the number of Is is zero (an
even number).
AC = 1 since there is a carry from D3 to D4.

DA instruction:
The DA (decimal adjust for addition) instruction will correct problem associated
with BCD addition. The DA instruction will add 6 to the lower nibble or higher nibble if
needed; otherwise, it will leave the result alone.

After the program is executed, register

A will contain 72H (47 + 25 = 72).
The “DA” instruction works
only on A.

Subtraction:

For subtraction only one instruction is used. To subtract without carry we have to make
CY = 0.
Example:

If the C Y = 0 after the execution

of SUBB, the result is positive; if
C Y = 1, the result is negative
and the destination has the 2′s
complement of the result. Normally, the result is left in 2′s complement, but the CPL
(complement) and INC instructions can be used to change it. The CPL instruction
performs the 1‘s complement of the operand; then the operand is incremented (INC) to
get the 2′s complement.

Multiplication:
The multiplication and division instructions work only with registers A and B. The
8051 supports byte-by-byte multiplication only.

Division:
The 8051 supports byte over byte division only.
When dividing a byte by a byte, the numerator
must be in register A and the denominator must
be in B. After the DIV instruction is performed, the quotient is in A and the remainder is
in B.
Example:

LOGIC AND COMPARE INSTRUCTIONS

1) AND:
Syntax:

This instruction will

perform a logical AND on
the two operands and place
the result in the
destination. The
destination is normally the
 accumulator. The source operand can be a register, in memory, or immediate.

2) OR:
Syntax: ORL destination, source; dest = dest OR source
The destination and source operands are ORed, and the result is placed in the
destination. The ORL instruction can be used to set certain bits of an operand to 1. The
destination is normally the accumulator. The source operand can be a register, in memory or
immediate.

3) XOR:
Syntax: XRL destination, source; dest = dest XOR source
This instruction will perform the XOR operation on the two operands, and place the
result in the destination. The destination is normally the accumulator. The source operand
can be a register, in memory, or immediate.
Example:

CPL A (complement accumulator):

This instruction complements the contents of register A. The complement action
changes the 0s to 1s and the 1s to 0s. This is also called 1’s complement. Although the CPL
instruction cannot be used to complement R0-R7, it does work on PO-P3 ports
Example: MOV A, #55H
CPL A ; A=AAH -01010101 becomes 10101010(AAH)
To get the 2′s complement, all we have to do is to add 1 to the 1’s complement.
Example:
 Compare instruction:
Syntax: CJNE destination,source,relative address
In the 8051, the actions of comparing and jumping are combined into a single
instruction called CJNE (compare and jump if not equal). The source operand can be in a
register, in memory, or immediate. The CJNE instruction compares two operands, and
jumps if they are not equal. This instruction affects the carry flag only.

Solution:
1. Yes, it jumps because 55H
and 99H are not equal.
2. A = 55H, its original value
before the comparison.

Rotate Instruction:
1) Rotating to right
Syntax: RR A; rotate right A
In rotate right, the 8 bits of the accumulator are rotated right one
bit, and bit DO exits from the
least significant bit and enters into D7 (most significant bit).

2) Rotating to left
 In rotate left, the 8 bits of the accumulator are
rotated left one bit, and bit D7 exits from the MSB
(most significant bit) and enters into DO (least
significant bit).

3) Rotating right through the carry

In RRC A, as bits are rotated from left to right,

they exit the LSB to the carry flag, and the carry flag enters the
MSB. In other words, in RRC A the LSB is moved to CY and
CY is moved to the MSB. In reality, the carry flag acts as if it is part of register A,
making it a 9-bit register.

4) Rotating left through the carry

In RLC A, as bits are shifted from right to

left they exit the MSB and enter the carry flag,
and the carry flag enters the LSB. In other
words, in RCL the MSB is moved to CY (carry flag) and CY is moved to the LSB.

SWAP A
It works only on the accumulator (A). It swaps the lower nibble and the higher
nibble. i.e. the lower 4 bits are put into the higher 4 bits, and the higher 4 bits are put into
the lower 4 bits.
 e.g.:

Loop and Jump Instructions:

Looping in the 8051

Repeating a sequence of instructions a certain number of times are called a loop.
In the 8051, the loop action is performed by the instruction “DJNZ reg, label”. In this
instruction, the register is decremented; if it is not zero, it jumps to the target address
referred to by the label.
e.g. MOV R0, #0FFH
Here: DJNZ R0, Here
End
Example:
In the example, the R2 register
is used as a counter. The counter is
first set to 10. In each iteration the
instruction DJNZ decrements R2 and
checks its value. If R2 is not zero, it
jumps to the target address associated
with the label “AGAIN”.
This looping action continues
until R2 becomes zero. After R2
becomes zero, it falls through the loop and executes the instruction
immediately below it, in this case the “MOV R5, A” instruction.
In the DJNZ instruction that the registers can be any of RO – R7.

Loop inside a loop (Nested loop) :

In 8051 the registers are 8-bit that can be count maximum of 256. For repeat an
action more times than 256, we use a loop inside a loop, i.e. nested loop. In a nested loop,
we use two registers to hold the count.
Example:
 Write a program to (a) load the accumulator with the value 55H, and (b)
complement the ACC 700 times.
Solution:
Since 700 is larger than 255 (the maximum capacity of any register), we use two
registers to hold the count. The following code shows how to use R2 and R3 for the
count.

In this program, R2 is used to keep the inner loop count. In the instruction “DJNZ
R2, AGAIN”, whenever R2 becomes 0 it falls through and “DJNZ R3, NEXT” is
executed. This instruction forces the CPU to load R2 with the count 70 and the inner loop
starts again. This process will continue until R3 becomes zero and the outer loop is
finished.

Other conditional jumps:

1) JZ (jump if A = 0)
In this instruction the content of register A is checked. If it is zero, it jumps to the target
address.
e.g.:

OVER: ----------
In this program, if either RO or Rl is zero, it jumps to the label OVER. Notice that
the JZ instruction can be used only for register A. It can only check to see whether the
accumulator is zero, and it does not apply to any other register.

Table: Conditional Jump

Instructions

All conditional jumps are short jumps,

meaning that the address of the target
must be within -128 to +127 bytes of the
contents of the program counter (PC).
Example:

Unconditional jump instructions:

In the 8051 there are two unconditional jumps: LJMP (long jump) and SJMP
(short jump).

1) LJMP (long jump):

LJMP is an unconditional long jump. It is a 3-byte instruction in which the first
byte is the opcode, and the second and third bytes represent the 16-bit address in range
0000 H to FFFFH.
e.g.: org 0000h
MOV A, #0FFH
LJMP $
-----------
$ : -----------
The program counter in the 8051 is 16-bit, hence it can access 64K bytes memory
but not all 8051 family members have 64K bytes of on-chip program ROM. Hence it is
necessary to save memory space. For this reason instead of LJMP instruction, SJMP
instruction is used which is a 2-byte instruction. This can save some bytes of memory in
many applications where memory space is in short supply. All conditional jumps such as
JNC, JZ, and DJNZ are also short jumps.

2) SJMP (short jump):

It is 2-byte instruction, the first byte is the opcode and the second byte is the
relative address of the target location. The relative address is in the range of 00 – FFH .It
is divided into forward and backward jumps; that is, within -128 to +127 bytes of
memory relative to the address of the current PC (program counter).
If the jump is forward, the target address can be within a space of 127 bytes from
the current PC. If the target address is backward, the target address can be within -128
bytes from the current PC.

Calculating the short jump address:

 All conditional jumps such as JNC, JZ, and DJNZ are also short jumps because
that they are all two-byte instructions. In these instructions the first byte is the opcode and
the second byte is the relative address.
The target address is relative to the value of the program counter. To calculate the
target address, the second byte is added to the PC of the instruction immediately below
the jump.

Example:
Using the following list file, verify the jump forward address calculation.

Solution:
A) Calculation of forward jumps:
1) First notice that the JZ and JNC instructions both jump forward.
2) The target address for a forward jump is calculated by adding the PC of the
following instruction to the second byte of the short jump instruction, which is called the
relative address.
3) In line 4 the instruction “JZ NEXT” has opcode of 60 and operand of 03 at the
addresses of 0004 and 0005.
4) The 03 is the relative address, relative to the address of the next instruction INC
RO, which is 0006. By adding 0006 to 3, the target address of the label NEXT, which is
0009, is generated.
5) In the same way for line 9, the “JNC OVER” instruction has opcode and
operand of 50 and 05 where 50 is the opcode and 05 the relative address.
6) Therefore, 05 is added, the address of instruction “CLR A”, giving 12H, the
address of label OVER.

B) Calculation of backward jumps:

1) In that program list, “JNC AGAIN” has opcode 50 and relative address F2H.
2) When the relative address of F2H is added to 15H, the address of the instruction
below the jump, we have 15H + F2H = 07 (the carry is dropped).
3) Notice that 07 is the address of label AGAIN. Look also at ‘.’SJMP HERE”,
which has 80 and FE for the opcode and relative address, respectively.
 4) The PC of the following instruction, 0017H, is added to FEH, the relative
address, to get 0015H, address of the HERE label (17H + FEH = 15H). Notice that FEH
is -2 and 17H + (-2) = 15

Call instruction:
The CALL instruction is used to call a subroutine. In the 8051 there are two call
instructions: LCALL (long call) and ACALL (absolute call).

LCALL (long call):

In this 3-byte instruction, the first byte is the opcode and the second and third
bytes are used for the address of the target subroutine. Therefore, LCALL can be used to
call subroutines located anywhere within the 64K-byte address space of the 8051.
When a subroutine is called, control is transferred to that subroutine, and the
processor saves the PC (program counter) on the stack and begins to fetch instructions
from the new location. After finishing execution of the subroutine, the instruction RET
(return) transfers control back to the caller. Every subroutine needs RET as the last
instruction.

Steps:
 1. Upon executing the first “LCALL DELAY”, the address of the instruction right
below it, “MOV A, #OAAH”, is pushed onto the stack, and the 8051 starts to execute
instructions at address 300H.
2. In the DELAY subroutine, first the counter R5 is set to 255 (R5 = FFH);
therefore, the loop is repeated 256 times. When R5 becomes 0, control falls to the RET
instruction, which pops the address from the stack into the program counter and resumes
executing the instructions after the CALL.

Call instruction and stack:

Upon calling a subroutine, the stack keeps track of where the CPU should return
after completing the subroutine. For this reason, we must be very careful in any
manipulation of stack contents. The rule is that the number of PUSH and POP
instructions must always match in any called subroutine. i.e. for every PUSH there must
be a POP.

Example:

ACALL (absolute call):

ACALL is a 2-byte instruction. The target address of the subroutine must be within 2K
bytes because only 11 bits of the 2 bytes are used for the address. ACALL is same as
LCALL it only saves ROM space.
Example: