XR

XTR111
T111

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Precision Voltage-to-Current
Converter/Transmitter
Check for Samples: XTR111

1FEATURES DESCRIPTION
2• EASY-TO-DESIGN INPUT/OUTPUT RANGES: The XTR111 is a precision voltage-to-current
0mA–20mA, 4mA–20mA, 5mA–25mA AND converter designed for the standard 0mA–20mA or
VOLTAGE OUTPUTS 4mA–20mA analog signals, and can source up to
• NONLINEARITY: 0.002% 36mA. The ratio between input voltage and output
current is set by the single resistor RSET. The circuit
• LOW OFFSET DRIFT: 1mV/°C can also be modified for voltage output.
• ACCURACY: 0.015%
An external P-MOSFET transistor ensures high
• SINGLE-SUPPLY OPERATION output resistance and a broad compliance voltage
• WIDE SUPPLY RANGE: 7V to 44V range that extends from 2V below the supply voltage,
• OUTPUT ERROR FLAG (EF) VVSP, to voltages well below GND.
• OUTPUT DISABLE (OD) The adjustable 3V to 15V sub-regulator output
• ADJUSTABLE VOLTAGE REGULATOR: provides the supply voltage for additional circuitry.
3V to 15V The XTR111 is available in MSOP and DFN
surface-mount packages.
APPLICATIONS 24V

• UNIVERSAL VOLTAGE-CONTROLLED 1
9
CURRENT SOURCE XTR111 VSP OD
8
Output Disable
REGF EF Output Failure
I- Mirror
• CURRENT OR VOLTAGE OUTPUT FOR 3-WIRE Regulator
5
IS 2
SENSOR SYSTEMS Out
REGS
15W
• PLC OUTPUT PROGRAMMABLE DRIVER 4 (1)

• CURRENT-MODE SENSOR EXCITATION Q2 S

Q1
3V VG 3 G
D

ISET
Signal 6 15W 10nF
Input VIN
Load 0mA to 20mA
4mA to 20mA

(± Load Ground)
GND SET
10 7
RSET IOUT = 10 (RVSET
VIN
)
IOUT = 10 · ISET

NOTE: (1) See Application Information,

External Current Limit Circuits for other
options.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
XTR111

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

PACKAGE
PRODUCT PACKAGE-LEAD DESIGNATOR PACKAGE MARKING
DFN-10 DRC BSV
XTR111
MSOP-10 DGQ CCM

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS (1) (2)

Over operating free-air temperature range (unless otherwise noted)

XTR111 UNIT
Power Supply Voltage, VVSP +44 V
Voltage at SET (3) –0.5 to +14 V
Voltage at IS (3) (4)
(VVSP) – 5.5 to (VVSP) + 0.5 V
Voltage at REGS, REGF, VIN, OD, EF –0.5 to (VVSP) + 0.5 V
Voltage at REGF, VG –0.5 to (VVSP) + 0.5 V
Current into any pin (3) (4) (5)
±25 mA
Output Short-Circuit Duration (6):
VG Continous to common and VVSP
REGF Continous to common and VVSP
Operating Temperature –55 to +125 °C
Storage Temperature –65 to +150 °C
Electrostatic Discharge Rating (HBM) 2000 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Refer to the Package Option Addendum at the end of this document for lead temperature ratings.
(3) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails must
be current limited.
(4) The IS pin current absolute maximum rating is +25mA and –50mA.
(5) See the following sections Explanation of Pin Functions, External MOSFET, and Voltage Regulator in Application Information regarding
safe voltage ranges and currents.
(6) See text in Application Information regarding safe voltage ranges and currents.

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ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range: TA = –40°C to +85°C.
All specifications at TA = +25°C, VVSP = +24V, RSET = 2.0kΩ, REGF connected to REGS; OD = Low, External FET connected,
unless otherwise noted.
XTR111
PARAMETER CONDITIONS MIN TYP MAX UNIT
TRANSMITTER
Transfer Function IOUT = 10 × VVIN/RSET
Specified Output Current IOUT Specified Performance (1) 0.1 25 mA
(2)
Derated Performance 0 to 36 mA
Current Limit for Output Current 42 ± 6 mA
(2) (3)
Nonlinearity, IOUT/ISET 0.1mA to 25mA 0.002 0.02 % of Span
0.1mA to 36mA 0.004 % of Span
(1)
Offset Current IOS IOUT = 4mA 0.002 0.02 % of Span
vs Temperature 0.0002 0.001 % of Span/°C
vs Supply, VVSP 8V to 40V Supply 0.0001 0.005 % of Span/V
(2)
Span Error, IOUT/ISET 0.1mA to 25mA 0.015 0.1 % of Span
vs Temperature (1) (2)
5 ppm/°C
vs Supply (1) 0.0001 % of Span/V
(4)
Output Resistance From Drain of QEXT >1 GΩ
Output Leakage OD = high <1 mA
Input Impedance (VIN) 2.4/30 GΩ/pF
Input Bias Current (VIN) IB 15 25 nA
(2)
Input Offset Voltage VOS VVIN = 20mV 0.3 1.5 mV
vs Temperature 1.5 mV/°C
Input Voltage Range (5) VVIN 0 to 12 V
(2)
Noise, Referred to Input 0.1Hz to 10Hz; IOUT = 4mA 2.5 mVPP
See Dynamic Performance
Dynamic Response
Section

(1) Includes input amplifier, but excludes RSET tolerance. Offset current is the deviation from the current ratio of ISET to IIS (output current).
(2) See Typical Characteristics.
(3) Span is the change in output current resulting from a full-scale change in input voltage.
(4) Within compliance range limited by (+VVSP – 2V) +VDS required for linear operation of QEXT.
(5) See Application Information, Input Voltage section.

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ELECTRICAL CHARACTERISTICS (continued)

Boldface limits apply over the specified temperature range: TA = –40°C to +85°C.
All specifications at TA = +25°C, VVSP = +24V, RSET = 2.0kΩ, REGF connected to REGS; OD = Low, External FET connected,
unless otherwise noted.
XTR111
PARAMETER CONDITIONS MIN TYP MAX UNIT
V-Regulator Output (REGF)
Voltage Reference (6) RLOAD = 5kΩ 2.85 3.0 3.15 V
vs Temperature (6) 30 ppm/°C
vs Supply (6) 0.1 mV/V
Bias Current into REGS (6) 0.8 mA
Load Regulation 0.6mA to 5mA 3 5 mV/mA
Supply Regulation (6) RLOAD = 5kΩ 0.01 mV/V
Output Current 5 mA
Short-Circuit Output Current 21 mA
DIGITAL INPUT (OD)
VIL Low-Level Threshold 0.6 V
VIH High-Level Threshold 1.8 V
Internal Pull-Up Current VOD < 5.5V 4 mA
DIGITAL OUTPUT (EF)
IOH Leakage Current (Open Drain) 1 mA
VOL Low-Level Output Voltage IEF = 2.2mA 0.8 V
IOL Current to 400mV Level VEF = 400mV 2 mA
POWER SUPPLY
Specified Voltage Range +8 +40 V
Operating Voltage +7 to +44 V
(6)
Quiescent Current IQ IOUT = 0mA 450 550 mA
TEMPERATURE RANGE
Specified Range –40 +85 °C
Operating Range –55 +125 °C
Package Thermal Impedance, qJA
DFN 70 °C/W
MSOP 63 °C/W

(6) See Typical Characteristics.

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PIN CONFIGURATIONS
DGQ PACKAGE DRC PACKAGE
MSOP-10 DFN-10
TOP VIEW TOP VIEW

VSP 1 Exposed 10 GND

Thermal VSP 1 Exposed 10 GND
IS 2 Die Pad 9 OD Thermal
on IS 2 Die Pad 9 OD
VG 3 8 EF
Underside. on
VG 3 8 EF
REGS 4 (Must be 7 SET Underside.
connected REGS 4 (Must be 7 SET
REGF 5 to GND) 6 VIN connected
REGF 5 to GND) 6 VIN

Pad

Pad

PIN DESCRIPTIONS
PIN NAME FUNCTION
1 VSP Positive Supply
2 IS Source Connection
3 VG Gate Drive
4 REGS Regulator Sense
5 REGF Regulator Force
6 VIN Input Voltage
7 SET Transconductance Set
8 EF Error Flag (Active Low)
9 OD Output Disable (Active High)
10 GND Negative Supply
Pad Pad Exposed Thermal Pad must be connected to GND

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TYPICAL CHARACTERISTICS
At TA = +25°C and VVSP = +24V, unless otherwise noted.
QUIESCENT CURRENT vs SUPPLY VOLTAGE QUIESCENT CURRENT vs TEMPERATURE
550 700
530 650
510
Quiescent Current (mA)

Quiescent Current (mA)

600
490
470 550

450 500
430 450
410
400
390
370 350

350 300
5 10 15 20 25 30 35 40 45 -75 -50 -25 0 25 50 75 100 125
Supply Voltage (V) Temperature (°C)

Figure 1. Figure 2.

GAIN vs FREQUENCY POWER-SUPPLY REJECTION RATIO vs FREQUENCY

40 140
See Applications Information, RSET = 2kW, No Bypass Cap
30 Dynamic Performance 120
RSET = 2kW, RLOAD = 2kW
20
RSET = 2kW, RLOAD = 600W 100
10
PSRR (dB)
Gain (dB)

RSET = 2kW, RLOAD = 200W 80

0
60
-10
40
-20

-30 20
Gain = VLOAD/VVIN
-40 0
1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)

Figure 3. Figure 4.

0.1Hz to 10Hz NOISE, RTI INPUT-REFERRED NOISE SPECTRUM

100m
IOUT = 4mA IOUT = 2mA

10m
IR Noise (VRMS/ÖHz)
1mV/div

1m

100n

10n
1s/div 1 10 100 1k 10k 100k
Frequency (Hz)

Figure 5. Figure 6.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and VVSP = +24V, unless otherwise noted.
NONLINEARITY DISTRIBUTION GAIN ERROR DISTRIBUTION
Population

Population

0.1
0.01
-0.1

-0.01
-0.001

0.01
-0.01

-0.03

0.02
-0.09

0.03

0.05

0.08
-0.05
-0.04

-0.02
-0.08
-0.07

0.04

0.06
0.07

0.09
-0.06
-0.007

-0.005
-0.008

-0.003
-0.006
-0.009

-0.002
-0.004

0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
0.009
0

Gain Error (%)

Nonlinearity (%)

Figure 7. Figure 8.

NONLINEARITY DRIFT DISTRIBUTION

NONLINEARITY vs TEMPERATURE (IOUT = 0.1mA to 25mA; T = –55°C to +125°C)
0.03

0.02
0.1mA to 25mA
Nonlinearity (%)

0.01
Population

4mA to 20mA
-0.01

-0.02

-0.03
-75 -50 -25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Temperature (°C) Nonlinearity Drift (ppm/°C)

Figure 9. Figure 10.

GAIN ERROR DRIFT DISTRIBUTION

GAIN ERROR vs TEMPERATURE (IOUT = 0.1mA to 25mA; T = –55°C to +125°C)
0.15

0.10

0.05
Gain Error (%)

Population

4mA to 20mA
0

-0.05
0.1mA to 25mA
-0.10

-0.15
-75 -50 -25 0 25 50 75 100 125 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0
Temperature (°C) Gain Error Drift (ppm/°C)

Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and VVSP = +24V, unless otherwise noted.
TYPICAL NONLINEARITY TYPICAL NONLINEARITY
(2pt Calibration at 4mA and 20mA) (2pt Calibration at 0.1mA and 25mA)
0.0020 0.0020

0.0015 0.0015

0.0010 0.0010

Nonlinearity (%)
Nonlinearity (%)

0.0005 0.0005

0.000 0.000

-0.0005 -0.0005

-0.0010 -0.0010

-0.0015 -0.0015

-0.0020 -0.0020
4 8 12 16 20 0 5 10 15 20 25
IOUT (mA) IOUT (mA)

Figure 13. Figure 14.

TYPICAL NONLINEARITY INPUT VOLTAGE RANGE LIMIT TO THE

(2pt Calibration at 0.1mA and 36mA) POSITIVE SUPPLY vs TEMPERATURE
0.010 3.0
Seven Typical Units Shown VVSP = 12V
0.008 2.9
0.006 2.8
Input Voltage Range Limit

0.004 2.7
Nonlinearity (%)

VVSP - VVIN (V)

0.002 2.6
0.000 2.5
-0.002 2.4
-0.004 2.3
-0.006 2.2
-0.008 2.1
-0.010 2.0
0 5 10 15 20 25 30 35 40 -75 -50 -25 0 25 50 75 100 125
IOUT (mA) Temperature (°C)

Figure 15. Figure 16.

OUTPUT SWING OF THE VOLTAGE ON IS PIN (VIS) OUTPUT SWING OF THE VOLTAGE ON IS PIN (VIS)
vs OUTPUT CURRENT vs TEMPERATURE
3.0 1.8

1.7
2.5
20mA
1.6
2.0
VVSP - VIS (V)

VVSP - VIS (V)

1.5
10mA
1.5 1.4

1.3
1.0 4mA
1.2
0.5
1.1

0 1.0
0 5 10 15 20 25 30 35 40 -75 -50 -25 0 25 50 75 100 125
Output Current (mA) Temperature (°C)

Figure 17. Figure 18.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and VVSP = +24V, unless otherwise noted.
INPUT OFFSET VOLTAGE DISTRIBUTION INPUT OFFSET VOLTAGE DRIFT DISTRIBUTION
Population

Population
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 -5 -4 -3 -2 -1 0 1 2 3 4 5
VOS (mV) VOS (mV/°C)

Figure 19. Figure 20.

INPUT OFFSET VOLTAGE vs SUPPLY VOLTAGE AMPLIFIER INPUT BIAS CURRENT vs TEMPERATURE
100 30
80 28
60 26
Input Offset Voltage (mV)

Input Bias Current (nA)

40 24
20 22
0 20
-20 18
-40 16
-60 14
-80 12
-100 10
0 10 20 30 40 50 -75 -50 -25 0 25 50 75 100 125
Supply Voltage (V) Temperature (°C)

Figure 21. Figure 22.

OUTPUT CURRENT LIMIT DISTRIBUTION OUTPUT CURRENT LIMIT vs TEMPERATURE

50
49
48
Current Limit (mA)

47
Population

46
45
44
43
42
41
40
51
37

41
36

38
39
40

42
43
44
45
46
47
48
49
50

52
53
54
55
56

-75 -50 -25 0 25 50 75 100 125

Current Limit (mA) Temperature (°C)

Figure 23. Figure 24.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and VVSP = +24V, unless otherwise noted.
REGULATOR VOLTAGE DISTRIBUTION REGULATOR VOLTAGE DRIFT DISTRIBUTION
ILOAD = 0.6mA ILOAD = 0.6mA
Population

Population
2.880
2.895
2.910
2.925
2.940
2.955
2.970
2.985

3.015
3.030
3.045
3.060
3.075
3.090
3.105
3.120
3.135
3.150
2.865
2.850

0 10 20 30 40 50 60 70 80 More
Regulator Voltage Drift (ppm/°C)
Regulator Voltage (V)

Figure 25. Figure 26.

REGULATOR INPUT REGULATOR INPUT BIAS

BIAS CURRENT DISTRIBUTION CURRENT DRIFT DISTRIBUTION
(Current into REGS Pin) (Drift of Current into REGS Pin)
Population
Population

3.2
0

2.8

4.0
0.4
0.8
1.2
1.6
2.0
2.4

3.6
-4.0

-3.2
-2.8
-2.4
-2.0
-1.6
-1.2
-0.8
-0.4
-3.6

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VREGS Input Bias Current (mA) VREGS Input Bias Current Drift (nA/°C)

Figure 27. Figure 28.

REGULATOR VOLTAGE vs SUPPLY VOLTAGE REGULATOR VOLTAGE vs TEMPERATURE

3.05 3.05
3.04 ILOAD = 0.6mA 3.04 ILOAD = 0.6mA

3.03 3.03
Regulator Voltage (V)
Regulator Voltage (V)

3.02 3.02
3.01 3.01
3.00 3.00
2.99 2.99
2.98 2.98
2.97 2.97
2.96 2.96
2.95 2.95
0 5 10 15 20 25 30 35 40 45 50 -75 -50 -25 0 25 50 75 100 125
Supply Voltage (V) Temperature (°C)

Figure 29. Figure 30.

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and VVSP = +24V, unless otherwise noted.
STEP RESPONSE: VFS = 4V, RSET = 2kΩ, RLD = 600Ω STEP RESPONSE: VFS = 2.5V, RSET = 1.25kΩ, RLD = 600Ω
(Rising Edge Depends on CGATE at VG Pin) (Rising Edge Depends on CGATE at VG Pin)

Photo taken with CGATE = 130pF Photo taken with CGATE = 130pF

5V/div 10V/div

5V/div 2V/div

10ms/div 10ms/div

Figure 31. Figure 32.

REGULATOR LOAD TRANSIENT REGULATOR LOAD TRANSIENT

(VREG Gain = 1V, VREGF = 3V, CL = 470nF, (VREG Gain = 4V, VREGF = 12V, CL = 470nF,
ILOAD = 3mA ± 0.3mA) ILOAD = 3mA ± 0.3mA)

2V/div
10mV/div

10mV/div

1V/div

40ms/div 40ms/div

Figure 33. Figure 34.

MAXIMUM REGULATOR CURRENT vs TEMPERATURE

29
Maximum Regulator Output Current (mA)

27

25

23

21

19

17

15
-75 -50 -25 0 25 50 75 100 125
Temperature (°C)
Figure 35.

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APPLICATION INFORMATION
used during power-on, multiplexing and other
The XTR111 is a voltage-controlled current source conditions where the output should present no
capable of delivering currents from 0mA to 36mA. current. It has an internal pull-up that causes the
The primary intent of the device is to source the XTR111 to come up in output disable mode unless
commonly-used industrial current ranges of the OD pin is tied low.
0mA–20mA or 4mA–20mA. The performance is
specified for a supply voltage of up to 40V. The The onboard voltage regulator can be adjusted
maximum supply voltage is 44V. The between 3V to 15V and delivers up to 5mA load
voltage-to-current ratio is defined by an external current. It is intended to supply signal conditioning
resistor, RSET; therefore, the input voltage range can and sensor excitation in 3-wire sensor systems.
be freely set in accordance with the application Voltages above 3V can be set by a resistive divider.
requirement. The output current is cascoded by an
Figure 36 shows a basic connection for the XTR111.
external P-Channel MOSFET transistor for large
The input voltage VVIN reappears across RSET and
voltage compliance extending below ground, and for
controls 1/10 of the output current. The I-Mirror has a
easy power dissipation. This arrangement ensures
precise current gain of 10. This configuration leads to
excellent suppression of typical interference signals
the transfer function:
from the industrial environment because of the
extremely high output impedance and wide voltage IOUT = 10 • (VVIN/RSET)
compliance.
The output of the voltage regulator can be set over
An error detection circuit activates a logic output the range of 3V to 12V by selecting R1 and R2 using
(error flag) in case the output current cannot correctly the following equation.
flow. It indicates a wire break, high load resistor, or VREGF = 3V · (R1 + R2)/R2
loss of headroom for the current output to the positive (1)
supply. The output disable (OD) provided can be

VVSP = 24V Supply

C1

1
9
VSP OD (Pull Low for Normal Operation)
REGF 8
EF
I-Mirror
5
IS 2

R1 15W
(1)
5.6kW
REGS
Q2 S
4 Q1
VG 3 G
D

3V 15W 10nF
R2
8.2kW
5V Load 0mA to 20mA
6 4mA to 20mA
VIN
(± Load Ground)
Signal
Source
(Sensor or
DAC, for
GND SET
example)
10 7

RSET IOUT = 10 ( RV )
VIN
SET

Figure 36. Basic Connection for 0mA to 20mA Related to 0V to 5V Signal Input. The Voltage Regulator is
Set to 5V Output

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EF : The active low error flag (logic output) is

EXPLANATION OF PIN FUNCTIONS intended for use with an external pull-up to logic-high
VIN: This input is a conventional, noninverting, for reliable operation when this output is used.
high-impedance input of the internal operational However, it has a weak internal pull-up to 5V and can
amplifier (OPA). The internal circuitry is protected by be left unconnected if not used.
clamp diodes to supplies. An additional clamp OD: This control input has a 4mA internal pull-up
connected to approximately 18V protects internal disabling the output. A pull-down or short to GND is
circuitry. Place a small resistor in series with the input required to activate the output. Controlling OD
to limit the current into the protection if voltage can be reduces output glitches during power-on and
present without the XTR111 being powered. Consider power-off. This logic input controls the output. If not
a resistor value equal to RSET for bias current used, connect to GND.
cancellation.
The regulator is not affected by OD.
SET: The total resistance connected between this pin
and VIN reference sets the transconductance.
Additional series resistance can degrade accuracy EXTERNAL CURRENT LIMIT
and drift. The voltage on this pin must not exceed The XTR111 does not provide internal current limit for
14V because this pin is not protected to voltages the case of when the external FET is forced to low
above this level. impedance. The internal current source controls the
current, but a high current from IS to GND forces an
IS: This output pin is connected to the transistor
internal voltage clamp between VSP and IS to turn
source of the external FET. The accuracy of the
on. This results in a low resistance path and the
output current to IS is achieved by dynamic error
current is only limited by the load impedance and the
correction in the current mirror. This pin should never
current capability of the external FET. A high current
be pulled more than 6.5V below the positive supply.
can destroy the IC. With the current loop interrupted
An internal clamp is provided to protect the circuit;
(the load disconnected) the external MOSFET is fully
however, it must be externally current-limited to less
turned on with large gate to source voltage stored in
than 50mA.
the gate capacitance. In the moment the loop is
VG: The gate drive for the external FET is protected closed (the load connected) current flows into the
against shorts to the supply and GND. The circuit is load. But for the first few micro-seconds the MOSFET
clamped so that it will not drive more than 18V below is still turned on and destructive current can flow,
the positive supply. The external FET should be depending on the load impedance.
protected if its gate could be externally pulled beyond
An external current limit is recommended to protect
its ratings.
the XTR111 from this condition. Figure 37a shows an
REGF: The output of the regulator buffer can source example of a current limit circuit. The current should
up to 5mA current, but has very limited (less than be limited to 50mA. The 15Ω resistor (R6) limits the
50mA) sinking capability. The maximum short-circuit current to approximately 37mA (33mA when hot). The
current is in the range of 15mA to 25mA, changing PNP transistor should allow a peak current of several
over temperature. hundred mA. An example device is the (KST)2907.
Power dissipation is not normally critical because the
REGS: This pin is the sense input of the voltage peak current duration is only a few micro-seconds.
regulator. It is referenced to an internal 3V reference However, observe the leakage current through the
circuit. The input bias current can be up to 2mA. Avoid transistor from IS to VG. The addition of this current
capacitive loading of REGS that may compromise the limiting transistor and R6 still require time to
loop stability of the voltage regulator. discharge the gate of the external MOSFET. R7 and
VSP: The supply voltage of up to a maximum of 44V C3 are added for this reason, as well as to limit the
allows operation in harsh industrial environment and steepness of external distortion pulses. Additional
provides headroom for easy protection against EMI and over-voltage protection may be required
over-voltage. Use a large enough bypass capacitor (> according to the application.
100nF) and eventually a damping inductor or a small Figure 37b is a universal and basic current limiter
resistor (5Ω) to decouple the XTR111 supply from the circuit, using PNP or NPN transistors that can be
noise typically found on the 24V supplies. connected in the source (IS to S) or in the drain
output (in series with the current path). This circuit
does not contribute to leakage currents. Consider
adding an output filter like R7 and C3 in this limiter
circuit.

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IS IS the OD pin high disables the gate driver and closes a

R6 R6 switch connecting an internal 3kΩ resistor from the
15W
15W VSP pin to the VG pin. This resistor discharges the
Q2 Q2 gate of the external FET and closes the channel; see
Q1 R7
VG 15W Q3
Figure 38.
IOUT R8

C3
5kW Table 1 lists some example devices in SO-compatible
10nF packages, but other devices can be used as well.
Q1 Avoid external capacitance from IS. This capacitance
VG
could be compensated by adding additional
capacitance from VG to IS; however, this
IOUT compensation may slow the output down.
a) Gate-Controlled Current Limit b) Serial Current Limit The drain-to-source breakdown voltage should be
selected high enough for the application. Surge
Figure 37. External Current Limit Circuits voltage protection might be required for negative
over-voltages. For positive over-voltages, a clamp
diode to the 24V supply is recommended, protecting
EXTERNAL MOSFET the FET from reversing.
The XTR111 delivers the precise output current to the
VSP
IS pin. The voltage at this pin is normally 1.4V below
VVSP. OD
16V
Switch
This output requires an external transistor (QEXT) that
forms a cascode for the current output. The transistor 3kW
must be rated for the maximum possible voltage on VG
VOUT and must dissipate the power generated by the
current and the voltage across it.
GND
The gate drive (VG) can drive from close to the
positive supply rail to 16V below the positive supply
voltage (VVSP). Most modern MOSFETs accept a Figure 38. Equivalent Circuit for Gate Drive and
maximum VGS of 20V. A protection clamp is only Disable Switch
required if a large drain gate capacitance can pulse
the gate beyond the rating of the MOSFET. Pulling

Table 1. P-Channel MOSFET (Examples) (1)

MANUFACTURER PART NO. BREAKDOWN VGS PACKAGE C-GATE
Infineon BSP170P –60V SOT-223 328pF
NEC 2SJ326-Z –60V Spec. 320pF
ON Semiconductor NTF2955 –60V SOT-223 492pF
Supertex Inc. TP2510 –100V TO-243AA 80pF

(1) Data from published product data sheet; not ensured.

14 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated

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 XTR111

www.ti.com SBOS375B – NOVEMBER 2006 – REVISED JUNE 2010

DYNAMIC PERFORMANCE The output glitch magnitude depends on the

mismatch of the internal current sources. It is
The rise time of the output current is dominated by approximately proportional to the output current level
the gate capacitance of the external FET. and scales directly with the load resistor value. It will
The accuracy of the current mirror relies on the differ slightly from part to part. The effects of filtering
dynamic matching of multiple individual current the output are shown in Figure 40 and Figure 41.
sources. Settling to full resolution may require a
complete cycle lasting around 100ms. Figure 39
shows an example of the ripple generated from the
individual current source values that average to the
specified accuracy over the full cycle.

External FET

No Filter
50mV/div

500W

20ms/div

Figure 39. Output Noise without Filter into 500Ω

External FET

Load Capacitor
50mV/div

CF
500W
10nF

20ms/div

Figure 40. Output with 10nF Parallel to 500Ω

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External FET

Typical Filter

5mV/div
RF
10kW

NOTE: Scale has been changed CF

500W
from Figure 38 and Figure 39. 10nF

20ms/div

Figure 41. Output with Additional Filter

OUTPUT ERROR FLAG AND DISABLE INPUT INPUT VOLTAGE

The XTR111 has additional internal circuitry to detect The input voltage range for a given output current
an error in the output current. In case the controlled span is set by RSET according to the transfer function.
output current cannot flow due to a wire break, high Select a precise and low drift resistor for best
load resistance or the output voltage level performance, because resistor drift directly converts
approaching the positive supply, the error flag (EF), into drift of the output current. Careful layout must
an open drain logic output, pulls low. When used, this also minimize any series resistance with RSET and the
digital output requires external pull-up to logic high VIN reference point.
(the internal pull-up current is 2mA).
The input voltage is referred to the grounding point of
The output disable (OD) is a logic input with RSET. Therefore, this point should not be distorted
approximately 4mA of internal pull-up to 5V. The from other currents. Assuming a 5V full-scale input
XTR111 comes up with the output disabled until the signal for a 20mA output current, RSET is 2.5kΩ. A
OD pin is pulled low. Logic high disables the output to resistance uncertainty of just 2.5Ω already degrades
zero output current. It can be used for calibration, the accuracy to below 0.1%.
power-on and power-off glitch reduction, and for
The linear input voltage range extends from 0V to
output multiplexing with other outputs connected to
12V, or 2.3V below the positive supply voltage
the same terminal pin.
(whichever is smaller). The lowest rated supply
Power-on while the output is disabled (OD = high) voltage accomodates an input voltage range of up to
cannot fully suppress output glitching. While the 5V. Potential clipping is not detected by an error
supply voltage passes through the range of 3V to 4V, signal; therefore, safe design guard banding is
internal circuits turn on. Additional capacitance recommended.
between pins VG and IS can suppress the glitch. The
Do not drive the input negative (referred to GND)
smallest glitch energy appears with the OD pin left
more than 300mV. Higher negative voltages turn on
open; for practical use, however, this pin can be
the internal protection diodes. Insert a resistor in
driven high through a 10kΩ resistor before the 24V
series with the input if negative signals can occur
supply is applied, if logic voltage is available earlier.
eventually during power-on or -off or during other
Alternatively, an open drain driver can control this pin
transient conditions. Select a resistor value limiting
using the internal pull-up current. Pull-up to the
the possible current to 0.3mA. Higher currents are
internal regulator tends to increase the energy
non-destructive (see Absolute Maximum Ratings), but
because of the delay of the regulator voltage
they can produce output current glitches unless in
increase, again depending on the supply voltage rise
disable mode.
time for the first few volts.

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 XTR111

www.ti.com SBOS375B – NOVEMBER 2006 – REVISED JUNE 2010

More protection against negative input signals is LEVEL SHIFT OF 0V INPUT AND
provided using a standard diode and a 2.2kΩ resistor, TRANSCONDUCTANCE TRIM
as shown in Figure 42.
The XTR111 offers low offset voltage error at the
input, which normally does not require cancellation. If
2.2kW
V-Signal VIN
the signal source cannot deliver 0V in a single-supply
circuit, an additional resistor from the SET pin to a
1N4148 positive reference voltage or the regulator output
(Figure 44) can shift the zero level for the input (VIN)
to a positive voltage. Therefore, the signal source can
drive this value within a positive voltage range. The
Figure 42. Enhanced Protection Against Negative example shows a +100mV (102.04mV) offset
Overload of VIN generated to the signal input. The larger this offset,
however, the more influence of its drift and
inaccuracy is seen in the output signal. The voltage at
4mA–20mA OUTPUT
SET should not be larger than 12V for linear
The XTR111 does not provide internal circuits to operation.
generate 4mA with 0V input signal. The most
Transconductance (the input voltage to output current
common way to shift the input signal is a two resistor
ratio) is set by RSET. The desired resistor value may
network connected to a voltage reference and the
be found by choosing a combination of two resistors.
signal source, as shown in Figure 43. This
arrangement allows easy adjustment for over-and
under-range. The example assumes a 5V reference XTR111
(VREF) that equals the full-scale signal voltage and a I-V Amp
signal span of 0V to 5V for 4mA to 20mA (IMIN to
IMAX) output. VIN

The voltage regulator output or a more precise

reference can be used as VREF. Observe the potential
drift added by the drift of the resistors and the voltage
reference. SET
120kW
5V +100mV
R1 Reference Offset
Reference 40kW RSET
Voltage 2kW
5V
VIN
R2 1V to 5V
Figure 44. Input Voltage Level Shift for 0mA
10kW
Input Voltage Output Current
0V to 5V

Figure 43. Resistive Divider for IMIN to IMAX Output

(4mA to 20mA) with 0V to VFS Signal Source

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SBOS375B – NOVEMBER 2006 – REVISED JUNE 2010 www.ti.com

VOLTAGE REGULATOR The voltage at REGF is limited by the supply voltage.

If the supply voltage drops close to the set voltage,
The externally adjustable voltage regulator provides the driver output saturates and follows the supply with
up to 5mA of current. It offers drive (REGF) and a voltage drop of less than 1V (depending on load
sense (REGS) to allow external setting of the output current and temperature).
voltage as shown in Figure 45. The sense input
(REGS) is referenced to 3.0V representing the lowest For good stability and transient response, use a load
adjustable voltage level. An external resistor divider capacitance of 470nF or larger. The bias current into
sets VREGF. the sense input (REGS) is typically less than 1mA.
VREGF = VREGS · (R1 + R2)/R2 This current should be considered when selecting
high resistance values for the voltage setting because
Table 2 provides example values for the regulator it lowers the voltage and produces additional
adjustment resistors. temperature dependence.
The REGF output cannot sink current. In case of
Table 2. Examples for the Resistor Values Setting supply voltage loss, the output is protected against
the Regulator Voltage the discharge currents from load capacitors by
VREGF (1) R1 R2 internal protection diodes; the peak current should not
3V 0 — exceed 25mA.
3.3V 3.3kΩ 33kΩ If the voltage regulator output is not used, connect
5V 5.6kΩ 8.2kΩ REGF to REGS (the 3V mode) loaded with a 2.2nF
12.4V 27kΩ 8.6kΩ capacitor. Alternatively, overdrive the loop pulling
(1) Values have been rounded.
REGS high (see Figure 45d).

REGF REGF
3V VREG

R1
REGS 470nF REG
5.6kW
REGS

470nF R2
8.2kW
3V
3V

(a) (b)

VSP

220W
1kW REGF REGF

R3
1kW 47kW
VREG 5V REGS
Source
R1
470nF
5.6kW
REGS
3V

R2
8.2kW

3V

(c) (d)

Figure 45. Basic Connections of the Voltage Regulator

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 XTR111

www.ti.com SBOS375B – NOVEMBER 2006 – REVISED JUNE 2010

APPLICATION BLOCK DIAGRAMS

1
VSP
OD 9

5 REGF Current EF 8
5V Mirror

C2 R1 IS 2
470nF 2kW
4 REGS 15W
(1)

R2 S
Q2
3kW Q1
VG 3 G
D
3V

15W 10nF
R3
12-Bit Digital-to-Analog 2.5kW 6 VIN
Digital I/O Converter
DAC7551

GND SET
10 7
0mA to 20mA
CLOAD RLOAD
RSET
2.5kW

Figure 46. Current Using 0V to 5V Input from a 12-Bit Digital-to-Analog Converter DAC7551

1
VSP
OD 9

5 REGF Current EF 8
5V Mirror
C2
470nF R1 IS 2
2kW
4 REGS
15W
(1)
REF3040 R2
4096mV Q2 S
3kW Q1
Voltage Reference VG 3 G
D
3V

15W 10nF
R3
16-Bit Digital-to-Analog 2kW 6 VIN
Digital I/O Converter
DAC8551

SET GND
7 10 0mA to 20mA output
R4 Load
for 10mV to 4096mV input
817.2kW
or a code of 160b to 65536b
CLOAD RLOAD
RSET
NOTE: Calculate RSET for R4 parallel to RSET. 2kW
(1.995kW)

Figure 47. Precision Current Output with Signal from 16-Bit DAC. Input Offset Shifted (R4) by 10mV for
Zero Adjustment Range

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SBOS375B – NOVEMBER 2006 – REVISED JUNE 2010 www.ti.com

1
VSP
OD 9

5 REGF Current EF 8
Mirror

IS 2

4 REGS 15W
(1)

Q2 S
Q1
VG 3 G
D
3V

15W 10nF

0V to 10V 6 VIN
Signal Input

GND SET
10 7 Load

SW1
RSET CLOAD RLOAD
5kW Current (open) or
Voltage (close) Output
When output disabled and SW1 is closed,
pin 7 may generate an error signal.

Figure 48. 0V to 10V or 0mA to 20mA Output Selected by Jumper (SW1)

(1)
(a) (b) R4
100W
+24V
Q2 Q2
NPN NPN

R3 R3
1kW 1kW
REGF REGF

R1
10kW
3V REGS 6V REGS
C2
470nF C2 R2
470nF 10kW

NOTE: (1) Resistor R4 can be calculated to protect Q2

from over current in fault conditions.

Figure 49. Voltage Regulator Current Boost Using a Standard NPN Transistor

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 XTR111

www.ti.com SBOS375B – NOVEMBER 2006 – REVISED JUNE 2010

PACKAGE AND HEAT SINKING NOTE: All thermal models have an accuracy variation
of 20%.
The dominant portion of power dissipation for the
current output is in the external FET. Component population, layout of traces, layers, and
air flow strongly influence heat dissipation.
The XTR111 only generates heat from the supply Worst-case load conditions should be tested in the
voltage with the quiescent current, the internal signal real environment to ensure proper thermal conditions.
current that is 1/10 of the output current, and the Minimize thermal stress for proper long-term
current and internal voltage drop of the regulator. operation with a junction temperature well below
The exposed thermal pad on the bottom of the +125°C.
XTR111 package allows excellent heat dissipation of
the device into the printed circuit board (PCB). LAYOUT GUIDELINES
The leadframe die pad should be soldered to a
THERMAL PAD thermal pad on the PCB. A mechanical data sheet
The thermal pad must be connected to the same showing an example layout is attached at the end of
voltage potential as the device GND pin. this data sheet. Refinements to this layout may be
required based on assembly process requirements.
Packages with an exposed thermal pad are Mechanical drawings located at the end of this data
specifically designed to provide excellent power sheet list the physical dimensions for the package
dissipation, but board layout greatly influences overall and pad. The five holes in the landing pattern are
heat dissipation. The thermal resistance from optional, and are intended for use with thermal vias
junction-to-ambient (TJA) is specified for the packages that connect the leadframe die pad to the heatsink
with the exposed thermal pad soldered to a area on the PCB.
normalized PCB, as described in Technical Brief
SLMA002, PowerPAD Thermally-Enhanced Package. Soldering the exposed pad significantly improves
See also EIA/JEDEC Specifications JESD51-0 to 7, board-level reliability during temperature cycling, key
QFN/SON PCB Attachment (SLUA271), and Quad push, package shear, and similar board-level tests.
Flatpack No-Lead Logic Packages (SCBA017). Even with applications that have low-power
These documents are available for download at dissipation, the exposed pad must be soldered to the
www.ti.com. PCB to provide structural integrity and long-term
reliability.

space
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (August, 2007) to Revision B Page

• Corrected errors in Figure 37 .............................................................................................................................................. 14

Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Link(s): XTR111
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

XTR111AIDGQR ACTIVE HVSSOP DGQ 10 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 CCM
& no Sb/Br)
XTR111AIDGQRG4 ACTIVE HVSSOP DGQ 10 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 CCM
& no Sb/Br)
XTR111AIDGQT ACTIVE HVSSOP DGQ 10 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 CCM
& no Sb/Br)
XTR111AIDGQTG4 ACTIVE HVSSOP DGQ 10 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 CCM
& no Sb/Br)
XTR111AIDRCR ACTIVE VSON DRC 10 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 BSV
& no Sb/Br)
XTR111AIDRCT ACTIVE VSON DRC 10 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 BSV
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
XTR111AIDGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
XTR111AIDGQT HVSSOP DGQ 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
XTR111AIDRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
XTR111AIDRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
XTR111AIDGQR HVSSOP DGQ 10 2500 370.0 355.0 55.0
XTR111AIDGQT HVSSOP DGQ 10 250 195.0 200.0 45.0
XTR111AIDRCR VSON DRC 10 3000 367.0 367.0 35.0
XTR111AIDRCT VSON DRC 10 250 210.0 185.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DRC 10 VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4204102-3/M
 PACKAGE OUTLINE
DRC0010J SCALE 4.000
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA

3.1
2.9

1.0 C
0.8

SEATING PLANE
0.05
0.00 0.08 C

1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED 4X (0.25)
THERMAL PAD

5 6

2X 11 SYMM
2
2.4 0.1

10
1
8X 0.5 0.30
10X
0.18
PIN 1 ID SYMM
0.1 C A B
(OPTIONAL)
0.5 0.05 C
10X
0.3

4218878/B 07/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(1.65)
(0.5)

10X (0.6)

1
10

10X (0.24)
11
SYMM (2.4)
(3.4)

(0.95)
8X (0.5)

5 6

(R0.05) TYP

( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND
EXPOSED METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4218878/B 07/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)
(0.5)
SYMM
EXPOSED METAL
11 TYP

10X (0.6)
1
10
(1.53)
10X (0.24) 2X
(1.06)

SYMM

(0.63)

8X (0.5)

6
5

(R0.05) TYP
4X (0.34)

4X (0.25)
(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4218878/B 07/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
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