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ARM Microprocessors Quiz Questions

ARM stands for Advanced RISC Machines (1). ARM microprocessors are designed for low cost, low power consumption, and mobile systems like handheld devices (2, 3). ARM uses 32-bit address spaces and supports both little-endian and big-endian addressing (5, 6). Memory in ARM systems can be accessed using load and store instructions (7).

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0% found this document useful (0 votes)
949 views4 pages

ARM Microprocessors Quiz Questions

ARM stands for Advanced RISC Machines (1). ARM microprocessors are designed for low cost, low power consumption, and mobile systems like handheld devices (2, 3). ARM uses 32-bit address spaces and supports both little-endian and big-endian addressing (5, 6). Memory in ARM systems can be accessed using load and store instructions (7).

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Pooja
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ARM MULTIPLE CHOICE

1. ARM stands for _____________ .


a) Advanced Rate Machines
b) Advanced RISC Machines
c) Artificial Running Machines
d) Aviary Running Machines
View Answer
2. The main importance of ARM micro-processors is providing operation with,
a) Low cost and low power consumption
b) Higher degree of multi-tasking
c) Lower error or glitches
d) Efficient memory management
View Answer
Answer:a
Explanation: The Stand alone feature of the ARM processors is that they’re economically
viable.
3. ARM processors where basically designed for _______ .
a) Main frame systems
b) Distributed systems
c) Mobile systems
d) Super computers
View Answer
Answer:c
Explanation: These ARM processors are designed for handheld devices.
4. The ARM processors doesn’t support Byte address ability ?
a) True
b) False
View Answer
Answer:b
Explanation: The ability to store data in the form of consecutive bytes.
5. The address space in ARM is ______ .
a) 2^24
b) 2^64
c) 2^16
d) 2^32
View Answer
Answer:d
Explanation: None.
6. The address system supported by ARM systems is/are ______ .
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both a and b
View Answer
Answer:d
Explanation: The way in which, the data gets stored in the system or the way of address
allocation is called as address system.
7. Memory can be accessed in ARM systems by _____ instructions .
i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
a) i,ii,iii
b) i,ii
c) i,iv,v
d) iii,iv,v
View Answer
Answer:b
Explanation: None.
8. RISC stands for _________ .
a) Restricted Instruction Sequencing Computer
b) Restricted Instruction Sequential Compiler
c) Reduced Instruction Set Computer
d) Reduced Induction Set Computer
View Answer
Answer:c
Explanation: This is a system architecture, in which the performance of the system is
improved by reducing the size of the instruction set.
9. In ARM, PC is implemented using ____ .
a) Caches
b) Heaps
c) General purpose register
d) Stack
View Answer
Answer:c
Explanation: PC is the place where the next instruction about to be executed is stored.
10. The additional duplicate register used in ARM machines are called as _______ .
a) Copied-registers
b) Banked registers
c) EXtra registers
d) Extential registers
View Answer
Answer:b
Explanation: The duplicate registers are used in situations of context switching.
11. The banked registers are used for,
a) Switching between supervisor and interrupt mode
b) Extended storing
c) Same as other general purpose registers
d) Both a and c
View Answer
Answer:a
Explanation: When switching from one mode to another, instead of storing the register
contents somewhere else it’ll be kept in the duplicate registers and the new values are
stored in the actual registers.
12. Each instruction in ARM machines is encoded into ____ Word .
a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte
View Answer
Answer:c
Explanation: The data is encrypted to make them secure.
13. All instructions in ARM are conditionally executed .
a) True
b) False
View Answer
Answer:a
Explanation: None.
14. The addressing mode where the EA of the operand is the contents of Rn is ______ .
a) Pre-indexed mode
b) Pre-indexed with write back mode
c) Post-indexed mode
d) None of the above
View Answer
Answer:c
Explanation: None.
15. The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is
_______ .
a) EA = [Rn]
b) EA = [Rn + Rm]
c) EA = [Rn] + Rm
d) EA = [Rm] + Rn
View Answer
Answer:a
Explanation: Effective address is the address that the computer acquires from the current
instruction being executed.

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