Data and Computer
Communications
Chapter 6 – Digital Data
Communications Techniques
* 1
Asynchronous and
Synchronous Transmission
timing problems require a mechanism to
synchronize the transmitter and receiver
● receiver samples stream at bit intervals
● if clocks not aligned and drifting will sample at
wrong time after sufficient bits are sent
two solutions to synchronizing clocks
● asynchronous transmission
● synchronous transmission
* 2
Asynchronous Transmission
* 3
Asynchronous - Behavior
simple
cheap
overhead of 2 or 3 bits per char (~20%)
good for data with large gaps (keyboard)
* 4
Synchronous Transmission
block of data transmitted sent as a frame
clocks must be synchronized
● can use separate clock line
● or embed clock signal in data
need to indicate start and end of block
● use preamble and postamble
more efficient (lower overhead) than async
* 5
Types of Error
an error occurs when a bit is altered between
transmission and reception
single bit errors
● only one bit altered
● caused by white noise
burst errors
● contiguous sequence of B bits in which first last and
any number of intermediate bits in error
● caused by impulse noise or by fading in wireless
● effect greater at higher data rates
* 6
Error Detection
will have errors
detect using error-detecting code
added by transmitter
recalculated and checked by receiver
still chance of undetected error
parity
● parity bit set so character has even (even
parity) or odd (odd parity) number of ones
● even number of bit errors goes undetected
* 7
Error Detection Process
* 8
Cyclic Redundancy Check
one of most common and powerful checks
for block of k bits transmitter generates an
n bit frame check sequence (FCS)
transmits k+n bits which is exactly divisible
by some number
receiver divides frame by that number
● if no remainder, assume no error
* 9
Modulo 2 Arithmetic (XOR)
Define:
● T = (k+n)-bit frame to be transmitted, n < k
● M = k-bit message, the first k bits of T
● F = n-bit FCS, the last n bits of T
● P = pattern of n+1 bits, the predetermined divisor
We would like T/P to have no remainder
● T = 2nM + F
● 2nM/P = Q + R/P, R is at least one bit less than P
● Use R as the FCS (i.e. F), i.e. T = 2nM + R
● Examine if T/P have no remainder?
*
• T/P = (2nM + R)/P = Q + R/P + R/P = Q + (R+R)/P = 10Q
Modulo 2 Arithmetic (cont)
Occurrence of errors
● Tr = T + E
● T = transmitted frame
● E = error pattern with 1s in positions of error
● Tr = received frame
Fail to detect an error if and only if Tr is
divisible by P
● i.e. if and only if E is divisible by P
* 11
Error Correction
correction of detected errors usually requires
data block to be retransmitted
not appropriate for wireless applications
● bit error rate is high causing lots of retransmissions
● when propagation delay long (satellite) compared with
frame transmission time, resulting in retransmission of
frame in error plus many subsequent frames
instead need to correct errors on basis of bits
received
error correction provides this
* 12
Error Correction Process
* 13
How Error Correction Works
adds redundancy to transmitted message
can deduce original despite some errors
eg. block error correction code
● map k bit input onto an n bit codeword
● each distinctly different
● if get error assume codeword sent was closest
to that received
for math, see Stallings chapter 6
means have reduced effective data rate
* 14
Line Configuration - Topology
physical arrangement of stations on
medium
● point to point - two stations
• such as between two routers / computers
● multi point - multiple stations
• traditionally mainframe computer and terminals
• now typically a local area network (LAN)
* 15
Line Configuration - Topology
* 16
Line Configuration - Duplex
classify data exchange as half or full duplex
half duplex (two-way alternate)
● only one station may transmit at a time
● requires one data path
full duplex (two-way simultaneous)
● simultaneous transmission and reception between
two stations
● requires two data paths
• separate media or frequencies used for each direction
● or echo canceling
* 17
Summary
asynchronous verses synchronous
transmission
error detection and correction
line configuration issues
* 18
