International Journal of Innovative Technology and Exploring Engineering (IJITEE)

ISSN: 2278-3075, Volume-8, Issue-6S3, April 2019

Advanced Rail Clamping PWM Techniques

based Three Level VSI fed DTC Induction
Motor Drive for THD and Common Mode
Voltage Reduction
C. Harinatha Reddy, K. SriGowri, T. Brahmananda Reddy, [Link] Kumar Yadav

Abstract— A space vector approach to advanced rail clamping operation. Multilevel inverters (MLI) are viable for
pulse width modulation methods (ARCPWM) is developed to resolving the above mentioned limitations as given in [1].
integrate direct torque control (DTC) scheme for the speed Research on two level VSI fed DTC IM drive is still
control of a three level inverter fed induction motor. In this
continued by many researchers towards development of
method the behavior of different ARCPWM methods is analyzed
with respect to zero state variation. It is observed that ARCPWM- switching control strategies for the decrease in torque ripple
3 shows reduction in both current harmonics as well as the in DTC, but for better performance of the drive presently
common mode voltage (CMV) during near rated speed operation concentration is on DTC systems employing multilevel
of the drive. To validate the proposed method a generalized topologies. Various topologies have been introduced and the
ARCPWM (GARCPWM) program is developed to generate most commonly used is the three-level neutral point
various ARCPWM methods using a constant variable ‘k’ that
clamped (NPC) VSI [2] that results in the increase of the
facilitates the instant of variation of zero state. Simulations
results for various ARCPWM controlled three level inverter fed number of voltage vectors and also good extent of increase
DTC induction motor drive are presented for comparing the in the number of possibilities in the vector selection process
performance in terms of total harmonic distortion of motor which in turn leads to considerable reduction of the torque
currents (𝑰𝑻𝑯𝑫 ) and CMV. and flux ripples. Also it has advantages like increment in
Index Terms—ARCPWM, CMV, DTC, GARCPWM, 𝑰𝑻𝑯𝑫 number of levels in the output voltage, less harmonic
distortion, and lower switching frequencies when compared
I. INTRODUCTION to two level VSI.
For the past few decades many industrial applications are Another important parameter in DTC IM drives that
driven by semi-automatic and fully automatic controlled causes damage to the IM is the Common Mode Voltage
machines, and especially induction motor (IM) control has (CMV) and is a source of electromagnetic interference that
been receiving superior attention because of the results in damage of machine windings insulation and
advancements in power electronics field. Development of bearings. To overcome this problem numerous pulse width
Field oriented control (FOC) of IM has enabled an AC modulation schemes have been proposed for VSI fed
motor to attain good dynamic responses as good as with DC Induction motor drives and however research on three level
motor and is based on control of stator current. Many VSI fed DTC IM drive is considered in this paper. Many
researchers worked on the problems associated with this researchers are paying attention towards high performance
control and Classical Direct Torque Control (CDTC) has PWM algorithms fed VSI fed DTC induction motor drive
emerged as an alternative to the well-known field oriented for better performance of the drive and some of them
control strategy for induction motor control and further presented their research as given in [3-4] and are restricted
better performance is achieved through Space vector to two level VSI fed only. However for three level VSI fed
Modulation techniques which is generally termed as DTC induction motor drives there are many control
conventional SVPWM based DTC(CSVPWMDTC). strategies as discussed in [4].
In general voltage source inverter (VSI) used for DTC IM For further improvement in performance of the drive
is the two-level VSI, that has number of inherent limitations mentioned above a reference voltage vector calculator is
and is traditional one. This VSI results in high distortion in employed for three level VSI fed DTC IM drive and is
the harmonics of output voltages and currents and also applied to various Space vector based PWM schemes to
includes large values of dV/dt in the output voltages, which avoid the use of hysteresis comparators and look up tables.
in turn results in deterioration of the machine performance Various Advanced rail clamping sequence based PWM
and considerable electromagnetic interference during (ARCPWM) schemes are employed to synthesize stator
voltage of an induction motor for the synchronized control
Revised Manuscript Received on April 12, 2019.
of torque and stator flux and are presented in this paper.
C. Harinatha Reddy, Associate Professor, EEE Department, G. Pulla Fig.1 is a diode clamped neutral point three level inverter
Reddy Engineering College(Autonomous), Kurnool, AP, India in which instantaneous voltage vectors possess redundancy
K. SriGowri, Professor, EEE Department,
[Link],(Autonomous), Kurnool, A.P., India
T. Brahmananda Reddy, Prof & Head, EEE Dept, G. Pulla Reddy
Engineering College,Autonomous),Kurnool,AP, India
[Link] Kumar Yadav, Assistant Professor, EEE Department, G.
Pulla Reddy Engineering College (Autonomous), Kurnool, AP, India

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Retrieval Number: F11290486S319/19©BEIESP 645 & Sciences Publication
 Advanced Rail Clamping PWM Techniques based Three Level VSI fed DTC Induction Motor Drive for
THD and Common Mode Voltage Reduction

characteristics that results in flexibility of inverter switching For synthesizing the Vref the number of steps in a three
mode selection. Due to this advantage in switching selection level inverter is the same as with the two level inverter and
control is done comfortably and hence performance can be is employed in the proposed algorithm. In order to achieve
improved for three level VSI fed DTC IM drive. For this the initial point of 𝑉𝑟𝑒𝑓 is shifted to the centre of the sub
validating the results a simulation programme has been hexagon in which 𝑉𝑟𝑒𝑓 is located as shown in Fig.3. The
developed. shifted reference vector 𝑉𝑟𝑒𝑓 ′
has 𝑉1 as initial point and is
making an angle 𝛽 with reference to 𝛼 axis. The time
duration for voltage vectors in order to get V’refi.e state 1
Sr1 Sy1 Sb1

Vdc/2
Sr2 Sy2 Sb2 (200), state 2 (210), and voltage vector state (100, 211) are
Vdc
R Y B obtained as T1, T2, and Tz, respectively and are given by
N
Sr3 Sy3 Sb3
(1)-(3). It is an added advantage in the design of PWM
Vdc/2 Sr4 Sy4 Sb4
techniques to have 𝑇𝑍 division between the two zero states.
0
Sin(60 −  )
T1 = M * * Ts
0
Fig. 1 Three level inverter Topology (Neutral Point Sin60 (1)
Clamped) fed IM. Sin( )

II. SPACE VECTOR APPROACH

T2 = M *
Sin 60 0 ( )
* Ts
(2)
TZ = Ts − T1 − T2
For a pulse width modulation technique in which space (3)
vector approach is employed, the reference voltage Here ‘M’ is the modulation index, given by
vector, 𝑉𝑟𝑒𝑓 (sample reference vector) is generated by Vref
maintaining the principle volt-second balance. Different Mi =
possible voltage vectors and their corresponding switching
2Vdc . (4)
states are represented on a three level 𝛼 − 𝛽 axis space
plane, shown in fig. 2. In a conventional two level inverter 110
221 V8 V13
for the instantaneous position and magnitude of 𝑉𝑟𝑒𝑓 the 210

nearest switching states are V0, V1, V2 and V0 as represented

in Fig. 3. When three level space plane is considered Vref
additional switching states are possible and the voltage V’ref

ripple can further be reduced by utilizing these additional

switching states. The nearest switching states with three 000
α 211
β
100
level inverter are V7, V1, V13 and V7. The switching states V0 V7 V1
200
with three level inversions are V7, V8, V9, V10, V11, and V12
and additional when compared to two level inverter. The
switching states and inverter switch positions of r-phase are
depicted in Table I.
Table I Switching states and their corresponding Pole 201
voltages 101 V12
212 V18
Switching state ON state devices Pole voltage
2 𝑆𝑟1 and 𝑆𝑟2 +𝑉𝑑𝑐 ⁄2 Fig. 3 Reference vector and shifted reference vector in
1 𝑆𝑟2 and 𝑆𝑟3 0 Sector-I of sub hexagon-I
0 𝑆𝑟3 and 𝑆𝑟4 -𝑉𝑑𝑐 ⁄2
The time durations for 0127, 012 and 721 sequences are
V3 V14 V2
220
shown in Fig.5. Equal division of 𝑇𝑍 results in lesser ripple
020
III 120
II current in lower modulation region and is used in
conventional space vector modulation to generate a given
021
V15
010
V9
121 221
V8
V13
210
sample in sector I. Only one zero state can also be used to
110 I
IV generate the sample as shown in fig. 4 i.e for the sequences
V4
Vref
V1
like 0121 and 7212 and this results in better performance i.e
022
011
V10
122
111
222
V
V00
000
α 211
V7
100
200
reduced current ripple when used in little higher modulation
region. Also sequences like 2721 or 1012 can be used to
generate the sample by considering the time division in to
V16
012 112
V11
001 101
V12
212
201 two equal intervals for one of the active vectors only. The
V18

V VI switching states placement and time division with 0127,

102 202
0121 and 7212 are shown in fig. 5.
V5
002 V17 V6

Fig.2. Three phase three level inverter switching states

and their corresponding voltage vectors. I, II, III, IV, V,
VI are the sectors.

Published By:
Blue Eyes Intelligence Engineering
Retrieval Number: F11290486S319/19©BEIESP 646 & Sciences Publication
 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-8, Issue-6S3, April 2019

III. CSVPWM ALGORITHM BASED THREE LEVEL The reduction in line current THD is based on the position
INVERTER FED DTC DRIVE: of clamping of the switching pulses. With ARCPWM1
The reference voltage vector is constructed by using the clamping takes place to positive dc rail in second half and
errors between the reference and actual d, q axes stator first half of sectors 1, 2 each for 300 and in sectors 6 and 1
fluxes and this is for controlling the torque and flux cycle- respectively. With ARCPWM2 pulses of r-phase clamps to
by-cycle. The block diagram of the proposed SVPWM negative dc rail from second half of sector 3 to first half of
based three level NPC fed DTC drive is as shown in Fig. 4. sector 5 leading to a continuous 1200 clamping. ARCPWM3
clamps for 1200 with 600 clamping to positive rail in sector 1
Vdc and 600 clamping to negative rail in sector 4. ARCPWM4
Te sl e e Vds

Reference clamps to positive dc rail in second half and first half of

3-level Inverter
PI PI
+ Voltage S
Ref
speed
+
_
Te r + Ve ctor V
P
sectors 1, 2 each for 300 and to negative dc rail in second half
+  *
s
Calculator W
and first half of sectors 4, 5 respectively leading to
M
_ Vqs*
Speed

s
V ds, Vqs continuous 600 clamping to positive rail and negative rail in
Calculation
each half of the fundamental cycle. ARCPWM5 generates
Adaptive split clamping pulses each clamping for 300 duration in first
Motor Model
2
3
half of sector 2, second half of sector 3, first half sector 5 and
second half of sector 6 in each fundamental cycle. With
IM
ARCPWM6 clamping takes place to positive dc rail in
Fig. 4 Block diagram of proposed CSVPWM based NPC second half and first half of sectors 6, 1 each for 300 and in
fed DTC-IM drive sectors 3 and 4 respectively. This is achieved by executing
the corresponding sequences as explained below.
IV. EXTENSION OF SPACE VECTOR APPROACH ARCPWM1 executes 7212 in all sectors and ARCPWM2
TO ARCPWM: executes 0121 in all sectors
The performance parameters considered for the validation ARCPWM3 executes 7212 in odd sectors and 0121 in
of the fact are THD in stator currents, line voltages, torque, even sectors and exactly opposite i.e. 0121 in odd sectors
flux ripple and CMV. In the Generalized Rail clamping and 7212 in even sectors will synthesize pulses for
PWM (GRCPWM) algorithm[5] the criteria of selection of ARCPWM5
zero states is only considered. However the degree of ARCPWM4 requires shifting of sequence 7212 to 0121
freedom of selection of active state along with zero state can exactly in the middle of odd sectors and 0121 to 7212 in
be utilized in other way. That is active state division along even sectors. Similarly if sequences are reversed the
with use of one zero state at any sampling time interval as algorithm generates ARCPWM6.
shown in Fig. 5 can also be considered for generation of Fig. [Link] the schematic diagrams of the instances of
various advanced rail clamping PWM methods (ARCPWM) generation of various ARCPWM methods where Z1-Z6 are
utilizing the same concept explained in GRCPWM. Since sectors
the algorithm is based on advanced rail clamping sequences
Z3 Z2 Z3 Z2

it is referred as GARCPWM. This is similar to the 7212 0121

GRCPWM algorithm in addition to zero state selection one

21

01
12

72

01

21
72

12

Z4 Z1
Z4 Z1

of the active states division (either active state 1 or active

01
72

21
12

21
12

01
72

7212 0121

state 2 in first sector) is considered for the generation of Z5

(a)
Z5

(b)
Z6

various ARCPWM methods. Also the present work Z3 Z2 Z3 Z2

considers equal division of active state time only. The 7212 0121
7212
01
12

21
72

21

01

placement of switching states for optimum performance is in

21

72

01

21
01

12

Z4 Z1 Z4 Z1
12
01

72
72
21

12

such a way that only one state transition must be there

12
72
21
72

0121
01
12

7212 0121

during state change. With the proposed three level inverter Z5

(c)
Z6 Z5

(d)
Z6

fed ARCPWM based DTC significant reduction in line Z3 Z2 Z3 Z2

0121 7212

current THD, torque and flux ripple, common mode 0121

72
21

12
01

12

72
12

01

72

12
72

21

voltages are observed. The different ARCPWM techniques Z4 Z1 Z4 Z1

21
72

01
01
12

21

21
01

considered are ARCPWM1, ARCPWM2, ARCPWM3,

12
01

7212
72
21

0121 7212
Z5 Z5
Z6
ARCPWM4, ARCPWM5 and ARCPWM6. (e) (f)
Z6

Fig. 6. Schematic diagrams showing the instances of

0 1 2 7 generation of various ARCPWM methods (a)
ARCPWM1 (b) ARCPWM2 (c) ARCPWM3 d)
0.5Tz T1 T2 0.5Tz
ARCPWM4 e) ARCPWM5 (f) ARCPWM6 where Z1-Z6
0 2 1 are sectors
1
Tz 0.5T1 T2 0.5T1

V. COMMON MODE VOLTAGE

7 2 1 2
The common mode voltage
Tz 0.5T2 T1 0.5T2
(CMV) is the voltage between
Fig. 5 CSVPWM and ARCPWM sequences
the centre of star connected

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 Advanced Rail Clamping PWM Techniques based Three Level VSI fed DTC Induction Motor Drive for
THD and Common Mode Voltage Reduction

point and the ground in a star connected 3-phase induction VII. RESULTS AND DISCUSSION
motor. For any star connected 3-phase induction motor the To verify the proposed ARCPWM schemes, numerical
CMV(Vcom) is given as simulation has been carried out in MATLAB/Simulink
Vao + Vbo + Vco environment. The average switching frequency of the
Vcom = Vso =
3 inverter is taken as 3KHz. Simulation results for different
(5)
ARCPWM based three level VSI fed DTC induction
V , V , Vco are inverter pole voltages. For a
where ao bo machine are given in Fig.8 to Fig.17. It can be observed that
balanced 3-phase supply this CMV is zero. But it changes among ARCPWM algorithms for three level VSI fed DTC
instantaneously whenever the drive is fed from an inverter. drive, the performance is significantly improved with the
The CMV depends on the switching states of the inverter proposed ARCPWM3 method in terms of torque and flux
and also its DC link voltage. Therefore the CMV changes ripple. Apart from these the common mode voltage is also
whenever the switching state is changed. The different shown in Fig 18 for all ARCPWM methods which depicts
switching states along with the associated CMVs are given the better values ARCPWM3 method employed. The line
in table 2.2. There will be no change in CMV if only even current THD is shown in Fig 7 and also the locus of flux
vectors or only odd vectors are used. When a change from ripple shown in Fig. 8. Table. 1 shows the comparison of
an even voltage vector to an odd voltage vector occurs, various ARCPWM methods with CSVPWMDTC method.
CMV of Vdc/3 is generated. If the change from an odd Among the various ARCPWM methods ARCPWM3 gives
vector voltage vector to the zero voltage vector occurs a less THD in line current along with common mode voltage.
CMV of 2Vdc/3 is generated which is the worst case. The overall behavior in terms of starting transients, steady
state. no-load behavior, transients during step change in load
VI. PROPOSED THREE LEVEL INVERTER FED and transients during reversal of speed is presented from
GARCPWM BASED DTC Fig. 9 to fig. 17. for all the ARCPWM methods that drive
the DTC induction motor. The harmonic spectral
The present section investigates the effect of variation of
performance is measured for steady state no-load condition
zero state and distribution of active states on the DTC
since the performance of any PWM method is judged by this
induction drive. A generalized algorithm to extract all the
and it agrees with ARCPWM3. The simulation parameters
advanced PWM methods is programmed in MATLAB to
are given in Annexure and results are given below.
synthesize required three level switching pulses. The pulses
are synthesized based on the selected PWM method, torque
SIMULATION PARAMETERS
and speed controller outputs. The speed controller generates
reference torque based on the error between reference speed 
Induction Motor Parameters: 3- , 400V, 4 kW, 4-pole,
and actual speed and error in torque generates reference slip 1470 RPM, 50 Hz,T=30 N-m
speed. Addition of reference slip speed with actual rotor
speed generates reference frequency. Stator Resistance, Rs 1.57 Ω
With inputs as reference flux magnitude and its rotating Rotor Resistance, Rr 1.21 Ω
speed, RFVC block will generate reference voltage vector to Magnetizing Inductance, Lm 0.165 H
synthesize three level output phase voltages to match the
Stator inductance, Ls 0.17 H
reference speed through GARCPWM algorithm.
Rotor inductance, Lr 0.17 H
GARCPWM is an m-file program developed in MATLAB
Moment of Inertia, J 0.089 Kg - m2
for easy implementation in any controller. Adaptive motor
Viscous friction coefficient, B 0 [Link]/rad
model takes motor voltages and currents as inputs and
estimates actual speed and torque. The overall block
diagram for executing the GARCPWM based three level
inverter fed induction motor drive is shown in Fig. 7.

Vdc
Te sl e e Vds
Reference A
PI
+
PI
+  Voltage R
Ref
_ C
speed Te r + Ve ctor
P
+  *
s
Calculator W
M
_ Vqs*
Speed
V ds, Vqs
s Calculation

Adaptive

3
Motor Model
2

Fig. 8 ARCPWM3-three-level VSI fed DTC: Harmonic

IM
Spectra of Line current
Fig. 7. Block diagram of GARCPWM based DTC
Induction motor drive

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 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-8, Issue-6S3, April 2019

Fig. 9 ARCPWM3-three-level VSI fed DTC: Stator flux

locus.

Fig. 11. ARCPWM3 based three level VSI fed DTC:

Pole, phase and line voltages, Line currents, speed,
torque and stator flux plots during steady state.
Fig. 10 ARCPWM3 based three level VSI fed DTC: Pole,
phase and line voltages, Line currents, speed, torque and
stator flux plots during transients.

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 Advanced Rail Clamping PWM Techniques based Three Level VSI fed DTC Induction Motor Drive for
THD and Common Mode Voltage Reduction

Fig. 12. ARCPWM3 based three level VSI fed DTC: Fig. 13. ARCPWM3 based three level VSI fed DTC:
Transients in pole, phase and line voltages, Line Transients in pole, phase and line voltages, line currents,
currents, speed, torque and flux during change in load: a speed, torque and stator flux during speed reversal:
30 N-m load is applied at 0.5 s and removed at 0.6 s speed is changed from +1400 rpm to -1400 rpm at 0.7 s
and from -1400 to +1400 at 1.3 s

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 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-8, Issue-6S3, April 2019

(a)

(b)

Fig.15. Comparison of THDs for various ARCPWMs

with CSVPWMDTC

(c)

Common mode Voltage

(d)

CSVPWM

ARCPWM2

ARCPWM5
ARCVPWM1

ARCPWM3

ARCPWM4

ARCPWM6
(e)

Fig. [Link] of common mode voltages for

various ARCPWM methods.

IX. CONCLUSIONS:

(f) From the results obtained in the previous sections for the
Fig 14. Common mode voltage waveforms during steady proposed three level VSI fed ARCPWM DTC drive, it is
state for (a) ARCPWM1, (b) ARCPWM2, (c) clear that the % THD of the line current in CSVPWM
ARCPWM3, (d) ARCPWM4, (e) ARCPWM5, (f) method are high compared to ARCPWM methods.
ARCPWM6 based three level VSI fed DTC IM drive. CSVPWM has highest THD of 4.75% for three level VSI
fed DTC where as ARCPWM methods have low THD’s
Table 1 Comparison of THDs in line currents and because of the better performance. There is a considerable
common mode voltage with various RCPWM, reduction in flux and torque ripple also. It has been proved
ARCPWMs integrated with two & three level inverter that by proper selection of zero state vectors and other
fed DTC Induction motor drive with respect to CDTC vectors and their time width, the amplitude of developed
and CSVPWM DTC torque also can be controlled. Therefore, control of flux and
[Link] torque is done separately. Also there is considerable
reduction in the common mode voltage by 33.33% for
ARCPWM3 method in comparison with CSVPWM method.
[Link] MethodThree level CMV for three
At the outset the overall performance of the drive operating
VSI fed level VSI fed DTC
at high modulation is noticeable with three level inverter
DTC IM IM drive (Peak to
controlled by ARCPWM3 method integrated with DTC
% THD of Peak Magnitude )
speed control technique.
line current in Volts
2 CSVPWM DTC 4.75 400
3 ARCPWM1 4.27 300
4 ARCPWM2 4.29 300
5 ARCPWM3 3.90 200
6 ARCPWM4 5.34 400
7 ARCPWM5 5.37 400
8 ARCPWM6 5.38 400

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 Advanced Rail Clamping PWM Techniques based Three Level VSI fed DTC Induction Motor Drive for
THD and Common Mode Voltage Reduction

X. REFERENCES
Tolbert, L.M., Peng, F.Z., and Habetler, T.G.:
‘Multilevel converters for large electric drives’, IEEE Trans.
Ind. Appl., 1999, 35, (1), pp.36-44.
1. Jose Rodriguez, Jih-Sheng Lai, Fang Zheng Peng: ‘Multilevel
Inverters: A Survey of Topologies, Control, and
Applications’, IEEE Trans. On Ind. Elec., Vol. 49, No. 4,
Aug. 2002.
2. C. Harinatha Reddy, T. Bramhananda Reddy, “ Generalized
Rail Clamping Sequences Based PWM (GRCPWM)
Algorithm for Direct Torque Controlled Induction Motor
Drive”, Journal of Control & Instrumentation ISSN: 2229-
6972 (Online), ISSN: 2347-7237 (Print) Volume 8,2018, Issue
3, pp. 38-59.
3. C. Harinatha Reddy, T. Bramhananda Reddy, “Advanced Rail
Clamping PWM Based Space Vector Algorithm for DTC
Induction Motor Drive”, Trends in Electrical Engineering
ISSN: 2249-4774 (Online), ISSN: 2321-4260 (Print) Volume
7, 2018, Issue 3, pp. 41-60.
4. C. Harinatha Reddy, T. Bramhananda Reddy, “Direct Torque
Control of Induction Motors Utilizing RCPWM Based Three-
Level Voltage Source Inverter”, IEEE International
Conference on Innovations in Engineering, Technology and
Sciences (ICIETS) 20th & 21st September 2018.

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