2019 3rd International Conference on Recent Developments in Control, Automation & Power Engineering (RDCAPE)

Design, Modeling and Performance of Static

Synchronous Series Compensator Regulated Self-
excited induction generator
Ashok Kumar1 Yogesh K Chauhan2* Ashish Shrivastava3
ashok47812@[Link] chauhanyk@[Link] [Link]@[Link]
1
Research Scholar, Deptt. of Electrical Engg. Dr. A.P.J Abdul Kalam Technical University, Lucknow, Uttar Pradesh
2*
Electrical Engineering Department, Kamla Nehru Institute of Tech. Sultanpur, U.P.-228118
3
Department of Electrical Engineering, Manipal University, Jaipur, Rajasthan

Abstract—Voltage regulation of Self-Excited Induction Generator The SSSC is a proven technology for transmission and
(SEIG) deteriorates with the inductive load and loading. In this distribution systems and is referred by various names such as
paper, the attempt is made to design, model and to improve the dynamic voltage restorer, series active filter, series active line
SEIG performance using self supported static synchronous series conditioner, static series compensator etc. [15-24]. The SSSC
compensator (SSSC). Contrary to series capacitor method, the consists of a three-phase, insulated gate bipolar transistors
performance with SSSC is extremely improved. The modeling of (IGBTs) based pulse width modulated (PWM), current
SEIG is done in q-d frame. The SSSC model is developed in abc controlled-voltage source converter (CC-VSC) with a capacitor
frame. The control technique of SSSC consists of dual or battery on dc bus. An insertion transformer is employed to
proportional-Integral (PI) controllers, one is applied to maintain
connect the SSSC in the system. It efficiently modulates the
dc link voltage by producing reference in-phae SSSC voltage and
resultant line impedance by producing a controllable voltage at
other PI controller is applied to maintain the load terminal
voltage by producing reference quadrature SSSC voltage.
suitable phase angle. Both real and reactive powers can be
Hysteresis current controller is applied to produce the pulses for exchanged with energy source on the dc link. When the
SSSC. The proposed control technique is simulated on developed injected voltage is in quadrature leading to the line current, it
model of SEIG-SSSC system. The system is tested for variety of emulates an inductor, otherwise a capacitor. In this paper, the
three-phase inductive load with sudden loading and unloading capacitor supported SSSC has been utilized for improvement of
conditions. The power quality of SEIG-SSSC system is also SEIG performance. The design, model and simulation of SSSC
assessed by evaluating harmonic spectrum of generator and load are detailed in the paper. The paper is outlined as, followed by
side voltage and current. The Total harmonic distortion (THD) of introduction in section 1, circuit description is discussed in
SEIG-SSSC system is obtained to comply the IEEE 519 standard. section 2, SSSC control model in section 3, load model in
Overall the system performance is found to be satisfactory. section 4, design steps for SSSC in section 5, results and
discussion in section 6; and finally conclusion in outlined in
Index Terms- Self-excited induction generator (SEIG); Series section 7.
compensation; Static synchronous series compensator (SSSC);
Voltage regulation of SEIG II. SYSTEM DESCRIPTION
I. INTRODUCTION
The system is described in Fig. 1. It composes of following
THE fossil fuels are depleting day by day. Further, they are components as,
causing environmental and ecological problems and
disturbances. Therefore, emphasis is given to utilize the • Three-phase star connected SEIG driven by a prime
renewable energy systems, which are neat and clean source of mover
energy, less impact on environment, ecological friendly, • Static R-L load
virtually low cost, and employment for electrical energy • Capacitor supported SSSC
generation. The induction generator, most suited for harnessing • Insertion transformer
small wind and hydro potential, has been researched • Associated control technique
enthusiastically in last four decades to tab the above advantages
[1-4]. However, the induction generator suffers from poor The operating function of SSSC is shown using phasor
frequency and voltage regulation. Numerous attempts are made diagram in Fig. 2. The SSSC ensures the load voltage to
to improve these for maturization of SEIG for industrial regulate to rated value during supply side disturbance and
application [5-8]. Development of power electronics switches voltage dip (Vg). During the voltage dip, the Vi is injected by
and various converters have extensively employed for SSSC, which thereby attains VL to rated value.
improvement of SEIG performance such as switched
capacitors, STATCOM, SSSC [9-14] etc.

978-1-7281-2068-3/19/$31.00 ©2019 IEEE 519

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 2019 3rd International Conference on Recent Developments in Control, Automation & Power Engineering (RDCAPE)

Vdc∗
V pl∗

vla∗ vlb∗ vlc∗

Vid∗
Viq∗
∗ ∗ ∗
(vida , vidb , vidc ) ∗
(viqa ∗
, viqb ∗
, viqc )

Figure 1. Schematic of complete system along with the control strategy

templates. The second PI controller is deployed on peak of

∗
load voltage (Vpl) and reference peak value ( Vpl ), which
maintains the load voltage by injecting the voltages in
quadrature. The output of this P-I controller is considered as
∗
peak quadrature SSSC voltage ( Viq ). The reference quadrature
∗ ∗ ∗
SSSC voltages ( viqa , viqb , viqc ) are obtained by multiplying
peak quadrature SSSC voltage with quadrature voltage
templates. The summation of the generated voltages (vga, vgb,
vgc), reference in-phase SSSC voltages and reference
quadrature SSSC voltages gives reference load voltages (
vla∗ , vlb∗ , vlc∗ ). The hysteresis controller is used for generating
Figure 2. System phasors under supply voltage dip the gating signals (Sa, Sb, Sc) for IGBTs of SSSC by comparing
actual and reference load voltages.
The proposed control technique consists of dual
proportional-integral (PI) controllers. First PI control is III. SSSC CONTROL MODEL
employed on DC bus voltage (Vdc) and its reference value ( The equations of SEIG are taken as usual q-d frame of
Vdc∗ ), which maintains the DC bus voltage by exchanging the reference and represented by five first order derivative
equations. The model of capacitor supported SSSC control
current to DC bus capacitor. This PI controller’s output is technique consists of equations for the following components.
∗
considered as peak in-phase SSSC voltage ( Vid ). The in-phase
• In-phase SSSC voltages
voltage templates (usda, usdb, usdc) are obtained using sensed • Quadrature SSSC Voltages
supply currents (isa, isb, isc) and quadrature current templates
• Reference Load Voltages
are derived using in-phase current templates. The reference in-
∗ ∗ ∗
• Hysteresis Controller
phase SSSC voltages (vida , vidc , vidc ) are obtained by • DC Bus Capacitor and Filter Inductor Current
multiplying peak in-phase SSSC voltage and in-phase voltage

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 2019 3rd International Conference on Recent Developments in Control, Automation & Power Engineering (RDCAPE)

A. In-Phase SSSC Voltages

ªusqa º ª 0 −1 3 1 3 º ªusda º
The output yvdc of PI controller yields reference peak in- « » « »« »
∗ u
« sqb » = « 3 2 1 2 3 −1 2 3 » «usdb » (6)
phase SSSC voltage Vid . The error evdc at nth instant is
«usqc » − 3 2 1 2 3 −1 2 3 » «¬usdc »¼
«
expressed as, ¬ ¼ «¬ »¼
∗ ∗ ∗
evdc (n) = Vdc∗ (n) − Vdc (n) The reference quadrature SSSC voltages ( viqa , viqb , viqc ) are
∗
yvdc (n) = yvdc (n − 1) + K pvdc (evdc (n) − evdc (n − 1)) + K ivdc eobtained
vdc ( n )
by multiplying Viq with quadrature voltage templates
(usqa, usqb, usqc) gives as,
= Vid∗ (1)
where, yvdc(n-1) and evdc(n-1) are the output and error at (n-1)th ªviqa
∗
º ªusqa º
sampling time respectively. « ∗ » ∗« »
The reference in-phase SSSC voltages are expressed using
«viqb » = Viq «usqb » (7)
« viqc
∗ » «usqc »
in-phase templates usda , usdb , u sdc as, ¬ ¼ ¬ ¼
C. Reference Load Voltages
ªvida
∗
º ªusda º These voltages are obtained as,
« ∗ » ∗ « »
« vidb » = Vid «usdb » (2)
ªvla∗ º ª vga º ªvida ∗
º ªviqa∗
º
« vidc
∗ »
«¬ usdc »¼ « ∗» « » « ∗ » « ∗ »
¬ ¼
«vlb » = « vgb » + « vidb » + « viqb » (8)
where usda , usdb and usdc are derived as, « vlc∗ » «ugc » « vidc∗ » « ∗ »
¬ ¼ ¬ ¼ ¬ ¼ ¬ viqc ¼
usda = isa I sm
D. Hysteresis Current Controller
usdb = isb I sm (3) The switching logic for ‘a’ phase of SSSC (Sa) is derived
∗
usdc = isc I sm using vla and vla as follows,

Ism, the peak supply current is computed as, If vla < ( vla∗ − HB ) S1 OFF, S 4 ON Ÿ S a = 0
1/ 2
­2 ½
¯3
(
I sm = ® isa2 + isb2 + isc2 ¾
¿
) (4) If vla > ( vla∗ + HB ) S1 ON, S 4 OFF Ÿ S a = 1
where, HB is the hysteresis limits. In similar manner, the
B. Quadrature SSSC Voltages logic for other phases may be derived.
This PI control is applied over reference peak load voltage
Vpl∗ and actual value Vpl sensed through load voltages. The PI
E. DC Bus Capacitor and Filter Inductor Current
controller’s output is yielded as reference peak quadrature
∗
Charging/discharging of DC link capacitor is derived by,
SSSC voltage ( Viq ). The voltage error evpl and output yvpl(n) at
nth sampling time are expressed as,
pVdc =
( ica Sa + icb Sb + icc Sc ) (9)
evpl (n) = V pl∗ (n) − V pl (n) Cdc

yvpl (n) = yvpl (n − 1) + K pvpl ( evpl (n) − evpl (n − 1) ) + K ivpl evlmac(nside

The DC bus voltage generates the voltages ea, eb and ec, on
) which as,
= Viq∗ (5) ªea º ª 2 −1 −1º ª Sa º
« e » = Vdc « −1 2 −1» « S » (10)
« b» 3 « »« b»
where, y(n-1) and e(n-1) are quantities at (n-1) sampling th
«¬ ec »¼ «¬ −1 −1 2 »¼ «¬ Sc »¼
time.
In-phase voltage templates are used to obtained Quadrature The filter inductor currents equations are denoted as,
( )
templates u sqa , u sqb , usqc as,

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 2019 3rd International Conference on Recent Developments in Control, Automation & Power Engineering (RDCAPE)

1 inductor results in sluggish response of the

pi fa =
Lf
( ea − via − R f i fa ) compensator. The inductance value depends upon
switching frequency fs and peak ripple current irpp with
linked ripple limits Krp. The inductor value [25] is
1
pi fb =
Lf
( eb − vib − R f i fb ) (11) therefore expressed using eq. (14) as,

§ 3·
1 ¨ ¸ vbat
pi fc =
Lf
( ec − vic − R f i fc ) Lf = © 2 ¹
(14)
6af s K rpirpp
where, ea, eb, ec are the ac side voltage of VSC; and via, vib, where, constant a lies between 1.2-2.0 to account for
vic are injected voltage into the supply lines. transient current and ripple band (Krp) =0.05-0.1.
The complete model of SSSC and its control are be • Filtering requirement of compensation voltage decides
expressed from eq. (1)-(11). the ripple filter capacitor Cf. Lower capacitance offers
large impedance to the fundamental frequency current
component and therefore reasonable value is selected
IV. RESISTIVE-INDUCTIVE LOAD to obtain good compensation voltage at fundamental
The state space current equations for star connected frequency. The natural frequency fn of L-C
resistive-inductive (Rl-Ll) load are written using eq. (12) as, combination is taken as the switching frequency fs
multiplied by Ksf [20]. The switching frequency is
1 varying in hysteresis current controller. The maximum
pila =
Ll
( vga − via − Rlila ) switching frequency is considered to be 10 kHz. The
natural frequency of L-C filter fn and switching
1 frequency fs are related using eq. (15) and (16) as,
pilb =
Ll
( vgb − vib − Rlilb ) (12)
1
fn = (15)
1 2π L f C f
pilc = ( vgc − vic − Rl ilc )
Ll f n = K sf f s (16)
where, via, vib, vic are injected voltages by SSSC.
The range of Ksf is 0.05-0.2.
V. DESIGN STEPS OF SSSC
The Cf can be obtained from equation (17) as.
A design methodology is proposed in this section for the
selection of SSSC parameters for capacitor supported SSSC 1
systems. Cf = (17)
( 2π K f )
2
sf s Lf
• . In the capacitor supported SSSC, the sizing of DC bus
capacitor is important because it acts as a DC source to • The performance of VSC depends on appropriate
provide real power exchange during transient series injection transformer. Selection of injection
conditions. The Cdc is calculated on the basis of energy transformer [20] is made, considering following points.
balance equation (13) as, • - It should possess low power loss, as the transformer
is permanently connected in the lines.
3Vl I l t
Cdc = (13) • - It should have small leakage reactance to result small
ª¬Vdcr
2
− Vdc2 º¼ non-sinusoidal voltage drop during the non-linear
where, Vl and Il are the load voltage and current current flowing through the transformer.
respectively, t is the response time of SSSC, Vdc and Vdcr are • It should have high operating frequency, as it has to
the actual and reference voltage on DC bus. reproduce the pulsating high switching frequency
• Maximum injection voltage and the current decide voltage of VSC.
volt-ampere (VA) of the SSSC. A margin of 10 %, is
considered to account for transients in supply current. • It should have VA rating higher than SSSC rating, It
although involves higher cost and larger size but the
• The main aim of L-C filter is to reduce the higher order transformer of lower VA rating may lead to saturation,
harmonics from the output. The inductor size governs overheating and improper operation of VSC.
the permissible ripples in the currents. Small inductor
results in high ripple content in the compensation • The SSSC device ratings depend upon type of the
voltage, and polluting the load voltage with high transformer. For the step up series transformer (step up
frequency switching harmonics. Whereas, the large the injected voltage to the supply side), the current
ratings of IGBTs and the ripple filter elements are to be

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 2019 3rd International Conference on Recent Developments in Control, Automation & Power Engineering (RDCAPE)

high whereas voltage rating is small and vice versa for The result of SEIG capacitor supported-SSSC supplying
the step down series transformer. 0.8 pf R-L load is illustrated in Fig. 3 using generator voltages
vgabc, generator currents igabc, load voltages vla, vlb, vlc, load
• On the basis of above factors, the volt-ampere (VA) currents ila, ilb, ilc, injected voltages via, vib, vic, peak load phase
rating of unity turn ratio insertion transformer is voltage Vpl, prime mover speed ωr, DC bus voltage Vdc. The 0.8
selected 20% over the VA rating of SSSC for pf load is increased from 1.0 kW to 2.0 kW at 1.2 sec., that
satisfactory performance.
results into increase in igabc and ila, ilb ilc; decrease in ωr. The
• The IGBTs are chosen for reasonable performance for load voltages (vla, vlb, vlc) stabilizes after experiencing three to
medium voltage and current range and operation in four cycles of disturbance. The Vdc also fluctuates around the
high switching frequency. Its voltage & current ratings reference value owing to discharging and charging of DC bus
are opted with the help of dc link votlage and SSSC capacitor. The load is decreased to 1.0 kW at 1.6 sec., that
rating with a factor, which accounts transient results into reduction in generator & load currents, rise in ωr.
conditions and safe operation of device. During This load voltage remains constant irrespective of the
increase or decrease of inductive load, which thereby shows the
The parameters of capacitor supported SSSC for feeding effectiveness of control technique.
0.8 pf static resistive-inductive load are mentioned in Table 1.
A. Harmonic Spectra of System Quantities
The generator and load, voltage and current of SEIG-SSSC
TABLE 1 CAPACITOR SUPPORTED SSSC DESIGN PARAMETERS system for R-L load in steady state are represented for three
R-L Load cycles and corresponding THD is shown in fig. 4 respectively.
SSSC Components
(0.8 pf, 2.0 kW)
SSSC kVA rating 2.426
THD in generator voltage & current is 1.12 and 1.76 %
Reference DC bus voltage (V) 350 respectively, whereas, load side voltage and current is having
DC bus capacitor (ȝF) 491.0 THD of 4.98 % and 3.24 % respectively.
Filter inductor (mH) 7.73
Filter capacitor (ȝF) 3.27 VII. CONCLUSION
Transformer kVA rating 2.668 Modeling, design and simulation of SEIG-capacitor
Selection of Device IGBT
supported SSSC system are presented for R-L load. The
Voltage rating of IGBT (V) 420
Current rating of IGBT (A) 4.62
proposed control technique for SSSC employs simple and easy
PI controller to derive the signals for gate drive. The control
technique of the SEIG-capacitor supported SSSC system
employed dual PI controllers. First PI controller is employed
VI. RESULTS AND DISCUSSION for maintaining DC bus voltage, whereas second one maintains
The specifications of the induction machine worked as the load voltage. The hysteresis current controller has been
SEIG, and gains of PI controllers used are shown below. used to produce the gating pulses for six IGBTs of SSSC.
Simulated characteristics for sudden increase and decrease of
3.7 kW, 415 V, Y-connected, 7.6 A cage induction machine the loads on SEIG have been studied to show the effectiveness
worked as Induction Generator, of control technique. The results show the satisfactory
performance of the complete system. The harmonics on
Tp = 6200 − 20ωr (Prime mover torque) generator side are well within the standard IEEE-519 limits for
Load voltage P-I controller gains SEIG-capacitor supported SSSC systems. For this, the
generator side harmonics are within 2%.
Kpvpl=0.00091; Kipvl=0.009190
DC bus P-I controller gains
Kpvdc=0.001; Kivdc=0.00070

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 2019 3rd International Conference on Recent Developments in Control, Automation & Power Engineering (RDCAPE)

vgabc (V)
500
0
-500
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
igabc (A) 20
0
-20
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
1000
vla (V)

0
-1000
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
1000
vlb (V)

0
-1000
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
1000
vlc (V)

0
-1000
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
10
ila (A)

0
-10
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
10
ilb (A)

0
-10
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
10
ilc (A)

0
-10
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
500
via (V)

0
-500
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
500
vib (V)

0
-500
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
500
vic (V)

0
-500
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
800
V pl (V)

600
400
200
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
ωr (Rad/s)

311
310
309
308
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
360
V dc (V)

350
340
330
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Time(sec)

Figure 3. Results of SEIG-SSSC supplying 0.8 pf R-L load

(Loading condition: Load raised from 1.0 kW to 2.0 kW at 1.2 sec. and subsequent reduced to 1.0 kW at 1.6 sec.)
THD of the waveform=1.12%
THD of the waveform=1.76%
300
8
400
10
200 6
200
v g a (V )

5
i g a (A )
vg a (V )

4
0
ig a (A )

100 0
-200 2
-5
0
-400 0 200 400 600 800 1000 0
1.4 1.41 1.42 1.43 1.44 1.45 1.46 -10 0 200 400 600 800 1000
Frequency (Hz) 1.4 1.41 1.42 1.43 1.44 1.45 1.46
Time(sec) Frequency (Hz)
Time(sec)
(a) (b)

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 2019 3rd International Conference on Recent Developments in Control, Automation & Power Engineering (RDCAPE)

THD of the waveform=4.98%

400 [10] Yogesh K Chauhan, Sanjay K Jain and Bhim Singh, “Transient Analysis
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200 [11] P. Singh and Yogesh K Chauhan, “Performance Analysis of Multi-Pulse
v la (V )

0
Electronic Load Controllers for Self-Excited Induction Generator”,
100 IEEE-International Conference on Energy Efficient Technologies for
-500
Sustainability (ICEETS13), 10-12 April, 2013, St. Xavier’s Catholic
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(c) communication technologies, 28-29 September, 2018, Galgotias
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10 6 STATCOM-based voltage regulator for self-excited induction
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[14] Yogesh K. Chauhan, Sanjay K Jain and Bhim Singh, “Static VAR
i la ( A )

i la (A )

0
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2 Components and Systems, vol. 36, no. 10, pp. 1080- 1101, 2008.
[15] R. K. Varma, S. Auddy and Y. Semsedini, “Mitigation of
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