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Analog ASSIGNMENT
BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI
Program: Work Integrated Learning Programme Division
Course Number MELZG632
Course Title Analog IC Design
Semester/Year Second Semester 2019-20
Instructor Dr. Saroj Mondal
Assignment No 2
Student Name MOHAMMAD RAHAMTULLA
Student ID 2019HT80542
Organization Redpine Signals India Pvt Ltd
Designation Engineering Manager
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Analog ASSIGNMENT
Note:
I have used 180nm node for simulator and LT Spice IV tool.
Title
Design an operational trans conductance amplifier with a voltage gain of 100 V/V, f-3 dB is 1 MHz, ICMR+ is 1.6 V and
ICMR- is 0.9 V. For design you may assume overdrive voltage is 0.2 V, CL = 5 pF, and use model parameters you
extracted in Assignment-1, experiment-1.
Circuit Diagram:
Design:
Given Specifications for Designed OTA
Gain 100V/V
f-3db 1Mhz
ICMR+ 1.6V
ICMR- 0.9V
Vov 0.2V
CL 5pf
Vdd = 1.8V
λn = 0.1335V-1
λp = 0.26V-1
μnCox = 2.8472x10-4
μpCox = 1.1052x10-4
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Analog ASSIGNMENT
Av = gm1,2 (r02 || r04)
f-3db = 1/2π(r02 || r04)CL
1Mhz = 1
2x(3.14)x(r02 || r04)x(5x10-12)
(r02 || r04) = 1
2x(3.14)x(10^6)x(5x10-12)
(r02 || r04) = 31.84 kΩ
Av = gm1,2 (r02 || r04)
100 = gm1,2 (31.84k)
gm1,2 = 100
31.84x10^3
= 3.140mS
(r02 || r04) = 31.84 kΩ
1 = 31.84K
gds2 + gds4
1 = 31.84K
Id2λn + Id4λp
Since Id2 = Id4
Id2(0.3998) = 10-3
31.84
Id2 = 10-3
31.84x0.3995
= 78.61uA
gm = 2µnCoxId(W/L)1
μnCox = 2.8472x10-4
(3.14x10-3)2 = 2x78.61x10-6x(2.8472x10-4) x (W/L)1,2
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Analog ASSIGNMENT
(W/L)1,2 = 9.85x10-6
4.49175x10-8
= 220
For M3,M4
ICMR+ = 1.6V
Vdd -|Vsg3| + Vth = 1.6
1.8 - |Vsg3|+ 0.476 = 1.6
|Vsg3| = 1.8-1.6+0.476
= 0.676V
|Vsg3| = Vth + 2Id / µpCox(W/L)3,4
(Vsg3 -Vth )2 = 2Id
μpCox(W/L)3,4
(0.676-0.476)
2 = 2x78.16x10-6
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(W/L)3,4 = 40
For M5:
Iss = 2Id
= 2x78.61x10-6
= 157.229uA
Given ICMR- = 0.9
Vth + (Vov)M1 + (Vgs5 -Vth) = 0.9
0.2V + Vgs5 = 0.9
Vgs5 = 0.7V
Iss = 0.5x μnCox (W/L)5(Vgs -Vth)2
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Analog ASSIGNMENT
(W/L)5 = 2Iss
μnCox(Vgs -Vth)2
= 2x157.229x10-6
(2.847x10-4)(0.7-0.5)2
= 26
Results and Observations:
Gain and phase plots are drawn and resulting gain in db is observed
from the ghaph
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Analog ASSIGNMENT
Above graph is when input is at 0.9V
Above graph is when input is at 1.6V
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Analog ASSIGNMENT
DC analysis:
For input at 0.9V
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Analog ASSIGNMENT
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Analog ASSIGNMENT
For input = 1.6V
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Analog ASSIGNMENT
Conclusion:
1) Single stage OTA is the basic configuration of the amplifiers we
had which has high input impedance
2) The design is less complex then other 2 stage OPAMPS
3) Can be used for low GBW requirement
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Analog ASSIGNMENT
Q2:
Title:
Design a two stage CMOS op-amp with AV = 5000V/V , GBW = 20MHz, CL = 10 pF, 0.9V ≤
ICMR ≤1.6V and P.M. = 60o. Use model parameters you extracted in Assignment-1,
experiment-1
Circuit:
Design:
Given Specifications for 2 stage Op-Amp
Gain 5000V/V
GBW 20Mhz
ICMR+ 1.6V
ICMR- 0.9V
PM 60
CL 10pf
Vdd = 1.8V
λn = 0.1335V-1
λp = 0.26V-1
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Analog ASSIGNMENT
μnCox = 2.8472x10 -4
μpCox = 1.1052x10-4
To get PM=60 degrees we are using
Cc = 0.22CL
gm6 = 10gm1
GBW = gm1/2πCc
Cc = 0.22X10pF = 2.2pf
GBW = 20x106 = gm1/2π2.2pf
gm1 = gm2 = 276.32us
gm6 = 10gm1
= 10x276.32
= 2.76ms
GBW = Av x BW
= 5000xBW
= 25
GBW = Av x BW
= 5000x BW
From here BW is calculated as
BW = 25.120K
P1 = BW = (gds2+gds4)(gds6+gds7)/Ccgm6
= 25.120x103
25.120x103 = (λnId2 + λpId4)(λnId6 + λpId7)/(2.2px2.76m)
Id2 = Id4 and Id6 = Id7 and Id6 = 10Id2
159.62x10-12 = 10x(0.399)2 x Id22
Id2 = 9.8uA
Id5 = 19.6uA
Id7 = 98uA
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Analog ASSIGNMENT
1) Calculation of (W/L)1
gm1 = 2µnCoxId(W/L)1
(276.32x10-6)2 = 2 x 9.8 x 10-6 x 300 x 10-6 x (W/L)1
(W/L)1 = 12.98 = (W/L)2
2) Calculation of M3,M4 with ICMR+
ICMR+ = Vdd - |Vsg3| + Vthp
1.6 = 1.8 - |Vsg3| + 0.476
|Vsg3| = 0.676
9.8x 10-6 = 1/2 x μpCox (W/L)3 (Vsg3 - Vth)2
9.8x 10-6 = 1/2 x 100x 10-6 (W/L)3 (0.2)2
(W/L)3,4 = 4.89
3) Calculation of M5 with ICMR-
ICMR- = 0.9
= Vthn + Vov)m1 + Vgs5 - Vth
Vgs5 = 0.7
(W/L)5 = 2Id
μnCox(Vgs-Vth)2
= 2 x 10.6 x 10-6
300x10-6x(0.2)2
= 3.27
Ibias = 20uA
4) Calculation of M6
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Analog ASSIGNMENT
To get maximum gain Vsg4 = Vsg6
gm= μnCox(W/L)(Vgs - Vth)
Vsg4 = 2 Id / upCox (W / L)4 + Vthp
gm6 = (W/L)6 x gm4
(W/L)4
gm4 = 2 x100 x10^ 6 x 4.89 x9.8 x10^ 6
gm4 = 97.79us
(W/L)6 = (W/L)4 x gm6/gm4
= 4.89x2.76x10-3
97.79x10-6
= 138
5) Calculation of M7
M8 is in current mirror with M8
I7/I5 = (W/L)7
(W/L)5
I6 = I7 = gm62
2μnCox(W/L)6
= (2.76x10-3)2
2x100x10-6x138
= 276.5 x10-6 x 3.27
19.6x10 -6
= 46
Therefore (W/L)7 = 46
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Analog ASSIGNMENT
Results and Observations:
When input is at 0.9V
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Analog ASSIGNMENT
When input is at 1.6V
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Analog ASSIGNMENT
DC analysis:
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Analog ASSIGNMENT
Conclusions:
As integrated circuit system are designed to appear as a single-pole system over a wide
frequency range to easy the problem that second order and greater system arises regarding
stability, compensation techniques must be improved to meet some design specification
constrains like higher unity gain frequency and better phase margin.
The analysis of design specifications for 2-stage CMOS Op Amp including simulation results
has done in this work. The mentioned results and graphs also depicted in the which estimates the
limits of scaling for several applications and devices. Designed Op Amp has high gain circuit for
the applications like comparators
The design of Op Amps basically considers, supply voltage and channel lengths of transistor
with era of CMOS technology with tradeoff among velocity, energy, gain and some other
parameters which signifies the performance
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Analog ASSIGNMENT
Question3:
Title:
Design a Telescopic Cascode OTA with a gain of 5000V/V, GBW =10MHz, CL = 10pF.
Circuit:
Design:
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Analog ASSIGNMENT
Given Av = 5000
GBW = 10Mhz
CL = 10pf
GBW = 10Mhz = gm12/2x3.14xCL
gm12 = 2x3.14x10x106 x 10 x 10-12
gm12 = 628us
Av = GmRout
Av = gm12(gm6r06r08 || gm4r04r02)
5000 = (628x10-6) Rout
Therefore Rout = 7.96Mohm
Swing:
Lets assume output is biased at Vdd/2 which is 1.8/2= 0.9V
So in order to overdrive headroom of M6 and M8
Vsdsat6 + Vsdsat8 = 0.45V
Similarly for M4, M2 and M0
Vsdsat4 + Vsdsat2 + Vsdsat0 = 0.450
Consider
M1-M4 are identical
M5-M8 are identical
From above conditions assumed M8 and M6 are identical
Vsdsat5-8 = 225mv
Similarly
Vsdsat1-4 = 150mv
gm1-4 = 2Id
Vsdsat1-4
628u = 2Id/(150x10-3)
Id1-4 = 628x10^-6x75x10-3
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Analog ASSIGNMENT
= 47.14uA
gm5-8 = 2Id5-2
Vsdsat5-8
= 2x47.1x10-6
225x10-3
gm5-8 = 418.66us
gm1-4 = 628us
λn = 0.1335V-1
λp = 0.26V-1
μnCox = 2.8472x10-4
μpCox = 1.1052x10-4
rds1-4 = 1/gds1-4
= 1/λnId1-4
= 1
0.1335x(47.1x10-4)
= 0.159MΩ
rds5-8 = 1/gds5-8
= 1/λnId5-8
= 1
0.2667x(47.1x10-4)
= 0.0795MΩ
Rout = r4p || rdn
rdn = =m1-4rds1-42
= (628x10-6)(0.159x106)2
= 15.87MΩ
rp = gm5-8rds5-82
= (418x10-6)(0.0759x106)2
= 2.64MΩ
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Analog ASSIGNMENT
So Rout = rdn || rp
= 2.26MΩ
DC gain = gm1Rout
= (628x10^-6)(2.26x10^6)
Av = 1419.28
Rout1 required = 5000/628x10^-6
= 7.9MΩ
If rup = rdn = 15.87MΩ then Rout1 is 8MΩ
Considering rup = rdn
(W/L)5-8 = (W/L)1-4x μnCox
μpCox
So rup = 15.87MΩ
So rds1-4 = 0.159MΩ
rds5-8 = 0.00795MΩ
Ratio = rds1-4/rds5-8
=2
(W/L)1-4 = (628x10^-6)2
2x300x10^-6x47.1x10^-6
= 14
So (W/L)5-8 = 14x(300/100)
= 42
So for M9 Vdsat = 150mv
And Id0 = 2x47.14
= 94.2uA
Id0 = 0.5unCoxW/L(Vdsat)2
(W/L)10,9 = 28
Given ICMR+ = 1.6
For M1 to be in saturation
ICMR = Vb2 - Vsg3 +Vth
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Analog ASSIGNMENT
1.6 = Vb2 + (150mv)
Vb2 = 1.45mV
Vb3 = 2Vov + Vth
= 2x225mv + 0.476
= 926mv
Results and Observations:
DC log:
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Analog ASSIGNMENT
AC analysis:
Conclusion:
1. From the theoretical study of telescopic presented in this paper, it is concluded that the overall
voltage swing of a folded-cascode op-amp is only slightly higher than that of a telescope
configuration. This advantage comes at the cost of higher power dissipation, lower voltage gain
and higher noise.
2. In telescopic op-amp, three voltage must be defined carefully, the input CM level and the gate
bias voltage of the PMOS and NMOS cascode transistors, whereas in folded-cascode
configurations only the latter two are critical.
