10/31/2020 ASIC-System on Chip-VLSI Design: Physical Design Interview Questions

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Below are the important interview questions for VLSI physical design aspirants. Are you interested to
Interview starts with flow of physical design and goes on.....on....on..... I am trying to write and publish
make your life easy..... let me prepare answers to all these if soft form.... as soon as it technology articles ?
happens those answers will be posted in coming blogs. asic-soc blog provides
reputed platform for
What parameters (or aspects) differentiate Chip Design & Block this. Your articles can
level design?? reach hundreds of
VLSI professionals.
How do you place macros in a full chip design?
Send your articles,
Differentiate between a Hierarchical Design and flat design? thesis, research
Which is more complicated when u have a 48 MHz and 500 MHz papers to:
[email protected]
clock design?
m
Name few tools which you used for physical verification?
What are the input files will you give for primetime correlation?
What are the algorithms used while routing? Will it optimize wire To subscribe asic-soc
length? blog enter your email
How will you decide the Pin location in block level design? address:

If the routing congestion exists between two macros, then what will
you do?
Subscribe
How will you place the macros?
How will you decide the die size? TOP POSTS

If lengthy metal layer is connected to diffusion and poly, then which

Backend (Physical
one will affect by antenna problem? Design) Interview
If the full chip design is routed by 7 layer metal, why macros are Questions and
Answers
designed using 5LM instead of using 7LM?
In your project what is die size, number of metal layers, Process-Voltage-
Temperature (PVT)
technology, foundry, number of clocks? Variations and
How many macros in your design? Static Timing
Analysis
What is each macro size and no. of standard cell count?
Clock Gating
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10/31/2020 ASIC-System on Chip-VLSI Design: Physical Design Interview Questions

How did u handle the Clock in your design?

What is the
What are the Input needs for your design? difference between
What is SDC constraint file contains? FPGA and ASIC?

How did you do power planning? Clock Definitions

How to find total chip power?
How to calculate core ring width, macro ring width and strap or READ MORE

trunk width? ASIC

How to find number of power pad and IO power pads? synthesis (38)
What are the problems faced related to timing? Synthesis
How did u resolve the setup and hold problem? (38) verilog
If in your design 10000 and more numbers of problems come, then interview
what you will do?
questions
In which layer do you prefer for clock routing and why? (30)
If in your design has reset pin, then it’ll affect input pin or output Verification
pin or both?
(28) ASIC
During power analysis, if you are facing IR drop problem, then how
(26) DSP (22)
did u avoid?
HDL (19) Static
Define antenna problem and how did u resolve these problem? Timing Analysis
How delays vary with different PVT conditions? Show the graph. (STA) (18) Low
Power Techniques
Explain the flow of physical design and inputs and outputs for each
(16) logic
step in flow. synthesis (16)
What is cell delay and net delay? FPGA (15)
What are delay models and what is the difference between them? MATLAB (15)
Timing Analysis
What is wire load model? (15) Physical
What does SDC constraints has? Design (13) Digital
design (9) CMOS (8)
Why higher metal layers are preferred for Vdd and Vss?
Asynchronous FIFO
What is logic optimization and give some methods of logic (7) interview (7) 3-D
optimization. ICs (6) PIC
What is the significance of negative slack? Microcontroller (6)
PIC 16F877A (5) VLSI
What is signal integrity? How it affects Timing? (4) Clock Gating (2)
What is IR drop? How to avoid .how it affects timing? EDA (2) Full Custom (2)
ASIC Jobs (1) AtopTech (1)
What is EM and it effects?
Gate Delay (1)
What is floor plan and power plan?
Articles
What are types of routing?
What is a grid .why we need and different types of grids? October 2007 (54)

What is core and how u will decide w/h ratio for core?
What is effective utilization and chip utilization?
What is latency? Give the types?

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10/31/2020 ASIC-System on Chip-VLSI Design: Physical Design Interview Questions

How the width of metal and number of straps calculated for power
and ground?
What is negative slack ? How it affects timing?
What is track assignment?
What is grided and gridless routing?
What is a macro and standard cell?
What is congestion?
Whether congestion is related to placement or routing?
What are clock trees?
What are clock tree types?
Which layer is used for clock routing and why?
What is cloning and buffering?
What are placement blockages?
How slow and fast transition at inputs effect timing for gates?
What is antenna effect?
What are DFM issues?
What is .lib, LEF, DEF, .tf?
What is the difference between synthesis and simulation?
What is metal density, metal slotting rule?
What is OPC, PSM?
Why clock is not synthesized in DC?
What are high-Vt and low-Vt cells?
What corner cells contains?
What is the difference between core filler cells and metal fillers?
How to decide number of pads in chip level design?
What is tie-high and tie-low cells and where it is used
What is LEF?
What is DEF?
What are the steps involved in designing an optimal pad ring?

What are the steps that you have done in the design flow?
What are the issues in floor plan?
How can you estimate area of block?
How much aspect ratio should be kept (or have you kept) and
what is the utilization?
How to calculate core ring and stripe widths?
What if hot spot found in some area of block? How you tackle this?
After adding stripes also if you have hot spot what to do?
What is threshold voltage? How it affect timing?
What is content of lib, lef, sdc?
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10/31/2020 ASIC-System on Chip-VLSI Design: Physical Design Interview Questions

What is meant my 9 track, 12 track standard cells?

What is scan chain? What if scan chain not detached and
reordered? Is it compulsory?
What is setup and hold? Why there are ? What if setup and hold
violates?
In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps,
Tsetup 50ps, tskew is 100ps. Then what is the maximum operating
frequency?
How R and C values are affecting time?
How ohm (R), fared (C) is related to second (T)?
What is transition? What if transition time is more?
What is difference between normal buffer and clock buffer?
What is antenna effect? How it is avoided?
What is ESD?
What is cross talk? How can you avoid?
How double spacing will avoid cross talk?
What is difference between HFN synthesis and CTS?
What is hold problem? How can you avoid it?
For an iteration we have 0.5ns of insertion delay and 0.1 skew and
for other iteration 0.29ns insertion delay and 0.25 skew for the
same circuit then which one you will select? Why?
What is partial floor plan?

Tags: Physical Design

5 comments:

Alexander November 16, 2007 at 3:06 PM

some of the Answers to these questions can be found at the below mentioned
location:
http://www.vlsichipdesign.com/asic_vlsi_faq/faq_page1.html

Visit this blog will try to answer one question daily

http://asicinterview.blogspot.com
Reply

Anil March 24, 2008 at 12:38 AM

Hi,

Do any one know the purpose of adding endcap cells?

Regards,
Anil
Reply

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10/31/2020 ASIC-System on Chip-VLSI Design: Physical Design Interview Questions

Replies

Unknown April 17, 2014 at 12:20 PM

for poly & nwell continuity purpose end caps are used.

Reply

Arun August 11, 2012 at 11:58 AM

End-cap cells are used to meet DRC rules in lower technology nodes.
Reply

Unknown February 16, 2016 at 10:54 AM

It's all about timing when it comes to best performing Chip design !!

https://www.udemy.com/vlsi-academy-sta-checks/?
couponCode=new_course_v2
Reply

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