Computer Architecture and Organization – I-MID-SEM
B Tech 3rd Semester
Marks: 20
Answer Q-1 and Q-2
Q-1. Select the most appropriate choice for any FIVE of the following
[2 X 5]
a) Which of the following are TRUE for number representation using 2’s complement scheme?
i. Only negative numbers have most-significant but as 1
ii. Equating an 8-bit number to a 16-bit destination must necessarily involve sign
extension
iii. Both i) and ii) above
iv. None of the above
b) In a typical carry-lookahead binary adder:
i. The 'propagate' and 'generate' signals play important roles
ii. Is significantly faster than ripple-carry adders where the width of the adder is high
iii. Can be implemented with a 'Lookahead Carry Unit' unit generating 'p' and 'g' signals
iv. All of the above
c) Nine (9) 3-8 decoders (and no other decoding logic) were used to connect 4KBytes static
RAM chips (i.e., the number of address input lines is 12 per chip, A 0 – A11) to fill up the entire
addressable space of a CPU. The number of address lines of the CPU is:
i. 16
ii. 18
iii. 20
iv. 24
d) In a cycle-stealing DMA scenario, there can be one byte of data transfer on the average per
instruction executed. The clock speed is 1Ghz and each instruction takes two clock cycle on
the average to execute. The time taken to transfer 1000 bytes of data in the scenario is:
i. 1 microsecond
ii. 2 microseconds
iii. 5 microseconds
iv. 0.5 microsecond
e) Suppose the occurrence of an interrupt is I, acknowledge of interrupts is A, servicing the
interrupt is S and return from interrupts is R and we arrange the events in time. Then
IASIASR means:
i. there was ONE interrupt which is being serviced now
ii. there were TWO interrupts and the second one is being serviced now by its service
routine
iii. there were TWO interrupts and the first one is being serviced now after returning
from the service routine of the first
iv. there were TWO interrupts and both of them have been serviced now by their
respective service routines
f) A device needs to send data to the computer about 100 times per second and during each
transfer about 4 bytes are sent. The best way to handle the situation is:
i. the device sends the data to a register and the underlying program reads the data
whenever it is free
ii. the device interrupts the CPU and the ISR reads in the data from the device in a
handshaking manner
iii. the device loads a FIFO buffer with the data to be send and then interrupts the CPU
and the ISR reads out the data from the FIFO
iv. such a situation is impossible to handle
g) A disk controller permits 40-bit wide linear-block addresses (LBA-s). Each block is 1-Kbyte in
size. The maximum storage supported by the disk controller is about:
i. 1 Gigabyte
ii. 1 Terrabyte
iii. 100 Terrabyte
iv. 1000 Terrabyte
h) Consider a machine with a byte addressable main memory of 2 32 bytes divided into blocks of
size 32 bytes. Assume that a direct mapped cache having 512 cache line is used with this
machine. The size of the tag filed in bits is:
i. 14
ii. 18
iii. 24
iv. 32
Q-2. [10]
Assume the array a (sized 10) as follows:
a[0] = 155, a[1] = 255, a[2] = 1, a[3] = 73, a[4] = 133, a[5] = 159, a[6] = 92, a[7] = 32, a[8] = 63,
a[9] = 216
First, write down the 'numbers' in order of appearance in your Roll Number followed by your
Registration number.
For example, if you have Roll: T91/IT/194113, Registration No: D01/1112/0188/19, then the
numbers to be written down are: 9,1,1,9,4,1,1,3,0,1,1,1,1,2,0,1,8,8,1,9
The answer to the assignment must be based on the above sequence of size 20. In case, the
size does not come up to 20, add randomly numbers between 0 and 9 to make it 20.
Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory
consists of 256 blocks and the request for memory blocks is in the order a[i], where i is number
taken from the list above, in order.
Thus, for the above list, you consider: a[9], a[1], a[1], a[9], a[4], ..., i.e., 216, 255, 255, 216, 133, ...
Find how blocks enter and are removed from the cache and hence determine which one of the
selected memory blocks will NOT be in cache at the end. LRU (least recently used) replacement
policy is used.
