FAN7930C — Critical Conduction Mode PFC Controller

FAN7930C
Critical Conduction Mode PFC Controller
Features Description
The FA N7930C is an active pow er factor correction
 PFC-Ready Signal
(PFC) controller for boost PFC applications that operate
 V IN-Absent Detection in critical conduction mode ( CRM). It uses a voltage-
mode PWM that compares an internal ramp signal w ith
 Maximum Sw itching Frequency Limitation
the error amplifier output to generate a MOSFET turn-off
 Internal Soft-Start and Startup w ithout Overshoot signal. Because the voltage- mode CRM PFC controller
does not need rectified A C line voltage infor mation, it
 Internal Total Harmonic Distortion (THD) Optimizer
saves the pow er loss of an input voltage-sensing netw ork
 Precise Adjustable Output Over-Voltage Protection necessary for a current-mode CRM PFC controller.
 Open-Feedback Protection and Disable Function FA N7930C provides over-voltage protection (OV P),
open-feedback protection, over-current protection
 Zero-Current Detector (ZCD)
(OCP), input-voltage-absent detection, and under-
 150 μs Internal Startup Timer voltage lockout protection ( UVLO). The PFC-ready pin
can be used to trigger other pow er stages w hen PFC
 MOSFET Over-Current Protection (OCP)
output voltage reaches the proper level w ith hysteresis.
 Under-Voltage Lockout w ith 3.5 V Hysteresis The FAN7930C can be disabled if the INV pin voltage is
low er than 0.45 V and the operating current decreases
 Low Startup and Operating Current to a very low level. Us ing a new variable on-time control
 Totem-Pole Output w ith High State Clamp method, total har monic distortion (THD) is low er than in
conventional CRM boost PFC ICs.
 +500/-800 mA Peak Gate Drive Current
 8-Pin, Small Outline Package (SOP) Related Resources
AN-8035 — Design Consideration for Boundary
Applications Conduction Mode PFC Using FAN7930
 Adapter
 Ballast
 LCD TV, CRT TV
 SMPS

Ordering Information

Part Number Operating Top Mark Package Packing

Temperature Range Method

FAN7930CMX-G -40 to +125°C 7930C 8-Lead, Small Outline Package (SOP) Tape & Reel

© 2010 Semiconductor Components Industries, LLC. Publication Order Number:

December-2017, Rev. 3 FAN7930C/D
 FAN7930C — Critical Conduction Mode PFC Controller
Application Diagram
DC OUTPUT

Vcc
FAN7930C
line filter 8 VCC 7
Out
5 ZCD
CS
4
AC INPUT 3 COMP
INV 1
2 RDY
GND

PFC 6
ready

Figure 1. Typical Boost PFC Application

Internal Block Diagram

VCC
H:open
VREF 2.5VREF 8 VCC
VCC
Internal
- VZ
VBIAS Bias reset
+
Clamp
Circuit

VTH(S/S)
8.5 12

ZCD 5 -
VCC
+ Restart
Timer Gate
VTH(ZCD)
Driver
7 OUT
fMAX
limit VO(MAX)
THD
Optimized S Q
Control Range
Sawtooth
Compensation
+
Generator
R Q
-
Startup without 40kW
Overshoot + 4 CS
8pF

-
INV 1 - VCS_LIM
VREF VREF
Stair +
6 GND
Step
Clamp
Circuit
reset
VIN Absent

COMP 3

disable
disable Thermal
Shutdown
- 0.35 0.45
2.5 2.675

+
RDY 2 INV_open
VBIAS
OVP
UVLO

2.051 2.240

Figure 2. Functional Block Diagram

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 FAN7930C — Critical Conduction Mode PFC Controller
Pin Configuration
VCC OUT GND ZCD

FAN7930C
8-SOP

INV RDY COMP CS

Figure 3. Pin Configuration (Top View )

Pin Definitions
Pin # Name Description

1 INV This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter
should be resistively divided to 2.5 V.
This pin is used to detect PFC output voltage reaching a pre-determined value. When output
2 RDY voltage reaches 89% of rated output voltage, this pin is pulled HIGH, w hich is an (open-drain)
output type.

3 COMP This pin is the output of the transconductance error amplifier. Components for the output voltage
compensation should be connected betw een this pin and GND.
This pin is the input of the over-current protection comparator. The MOSFET current is sensed
4 CS using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is
included to filter sw itching noise.

5 ZCD This pin is the input of the zero-current detection (ZCD) block. If the voltage of this pin goes
higher than 1.5 V, then goes low er than 1.4 V, the MOSFET is turned on.
This pin is used for the ground potential of all the pins. For proper operation, the signal ground
6 GND
and the pow er ground should be separated.
This pin is the gate drive output. The peak sourcing and sinking current levels are +500 mA and
7 OUT -800 mA, respectively. For proper operation, the stray inductance in the gate driving path must be
minimized.
8 V CC This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.

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 FAN7930C — Critical Conduction Mode PFC Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

V CC Supply Voltage VZ V
IOH, IOL Peak Drive Output Current -800 +500 mA
ICLAMP Driver Output Clamping Diodes V O>V CC or V O<-0.3 V -10 +10 mA
IDET Detector Clamping Diodes -10 +10 mA
( )
RDY Pin 1 VZ
( )
V IN Error Amplifier Input, Output and ZCD 1 -0.3 8.0 V
( )
CS Input Voltage 2 -10.0 6.0
TJ Operating Junction Temperature +150 °C
TA Operating Temperature Range -40 +125 °C
TSTG Storage Temperature Range -65 +150 °C

Electrostatic Discharge Human Body Model, JESD22-A114 2.5

ESD kV
Capability Charged Device Model, JESD22-C101 2.0
Notes:
1. When this pin is supplied by external pow er sources by accident, its maximum allow able current is 50 mA.
2. In case of DC input, the acceptable input range is -0.3 V~6 V: w ithin 100 ns -10 V~6 V is acceptable, but
electrical specifications are not guaranteed during such a short time.

Thermal Impedance
Symbol Parameter Min. Max. Unit
( )
JA Thermal Resistance, Junction-to-Ambient 3 150 °C/W
Note:
3. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.

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 FAN7930C — Critical Conduction Mode PFC Controller
Electrical Characteristics
V CC = 14 V and TA = -40°C~+125°C, unless otherw ise specified.

Symbol Parameter Conditions Min. Typ. Max. Unit

V CC Section
V START Start Threshold Voltage V CC Increasing 11 12 13 V
V STOP Stop Threshold Voltage V CC Decreasing 7.5 8.5 9.5 V
HY UVLO UVLO Hysteresis 3.0 3.5 4.0 V
VZ Zener Voltage ICC=20 mA 20 22 24 V
V OP Recommended Operating Range 13 20 V
Supply Current Section
ISTART Startup Supply Current V CC=V START-0.2 V 120 190 µA
IOP Operating Supply Current Output Not Sw itching 1.5 3.0 mA
IDOP Dynamic Operating Supply Current 50 kHz, CI=1 nF 2.5 4.0 mA
IOPDIS Operating Current at Disable V INV=0 V 90 160 230 µA
Error Am plifier Section
V REF1 Voltage Feedback Input Threshold1 TA=25°C 2.465 2.500 2.535 V
V REF1 Line Regulation V CC=14 V~20 V 0.1 10.0 mV
( )
V REF2 Temperature Stability of V REF1 4 20 mV
IEA,BS Input Bias Current V INV=1 V~4 V -0.5 0.5 µA
IEAS,SR Output Source Current V INV=V REF -0.1 V -12 µA
IEAS,SK Output Sink Current V INV=V REF +0.1 V 12 µA
V EAH Output Upper Clamp Voltage V INV=1 V, V CS=0 V 6.0 6.5 7.0 V
V EAZ Zero-Duty Cycle Output Voltage 0.9 1.0 1.1 V
( )
gm Transconductance 4 90 115 140 µmho
Maxim um On-Tim e Section
tON,MAX1 Maximum On-Time Programming 1 TA=25°C, V ZCD=1 V 35.5 41.5 47.5 µs

tON,MAX2 Maximum On-Time Programming 2 TA=25°C, 11.2 13.0 14.8 µs

IZCD=0.469 mA
Current-Sense Section
Current-Sense Input Threshold
V CS 0.7 0.8 0.9 V
Voltage Limit
ICS,BS Input Bias Current V CS=0 V~1 V -1.0 -0.1 1.0 µA

tCS,D Current-Sense Delay to Output

(4) dV/dt=1 V/100 ns, 350 500 ns
from 0 V to 5 V

Continued on the following page…

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 FAN7930C — Critical Conduction Mode PFC Controller
Electrical Characteristics
V CC = 14 V and TA = -40°C~+125°C, unless otherw ise specified.

Symbol Parameter Conditions Min. Typ. Max. Unit

Zero-Current Detect Section
( )
V ZCD Input Voltage Threshold 4 1.35 1.50 1.65 V
( )
HY ZCD Detect Hysteresis 4 0.05 0.10 0.15 V
V CLAMPH Input High Clamp Voltage IDET=3 mA 5.5 6.2 7.5 V
V CLAMPL Input Low Clamp Voltage IDET= -3 mA 0 0.65 1.00 V
IZCD,BS Input Bias Current V ZCD=1 V~5 V -1.0 -0.1 1.0 µA
( )
IZCD,SR Source Current Capability 4 TA=25°C -4 mA
( )
IZCD,SK Sink Current Capability 4 TA=25°C 10 mA

tZCD,D Maximum Delay From ZCD to Output dV/dt=-1 V/100 ns, from 100 200 ns
( )
Turn-On 4 5 V to 0 V
Output Section
V OH Output Voltage High IO=-100 mA, TA=25°C 9.2 11.0 12.8 V
V OL Output Voltage Low IO=200 mA, TA=25°C 1.0 2.5 V
( )
tRISE Rising Time 4 CIN=1 nF 50 100 ns
( )
tFALL Falling Time 4 CIN=1 nF 50 100 ns
V O,MAX Maximum Output Voltage V CC=20 V, IO=100 µA 11.5 13.0 14.5 V
V O,UVLO Output Voltage w ith UVLO Activated V CC=5 V, IO=100 µA 1 V
Restart / Maxim um Sw itching Frequency Lim it Section
tRST Restart Timer Delay 50 150 300 µs
( )
f MAX Maximum Sw itching Frequency 4 250 300 350 kHz
RDY Pin
IRDY,SK Output Sink Current 1 2 4 mA
V RDY,SAT Output Saturation Voltage IRDY,SK=2 mA 320 500 mV
IRDY,LK Output Leakage Current Output High Impedance 1 µA
Soft-Start Tim er Section
( )
tSS Internal Soft-Soft 4 3 5 7 ms
UVLO Section
V RDY Output Ready Voltage 2.166 2.240 2.314 V
HY RDY Output Ready Hysteresis 0.189 V
Protections
V OVP OVP Threshold Voltage TA=25°C 2.620 2.675 2.730 V
HY OVP OVP Hysteresis TA=25°C 0.120 0.175 0.230 V
V EN Enable Threshold Voltage 0.40 0.45 0.50 V
HY EN Enable Hysteresis 0.05 0.10 0.15 V
( )
TSD Thermal Shutdow n Temperature 4 125 140 155 °C
( )
THYS Hysteresis Temperature of TSD 4 60 °C
Note:
4. These parameters, although guaranteed by design, are not production tested.

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 FAN7930C — Critical Conduction Mode PFC Controller
Comparison of FAN7530 and FAN7930C
Function FAN7530 FAN7930C FAN7930C Advantages
 No External Circuit for PFC Output UVLO

PFC Ready Pin None Integrated

 Reduce Pow er Loss and BOM Cost Caused by
PFC Out UVLO Circuit
 Versatile Open-Drain Pin
 Abnormal CCM Operation Prohibited
Frequency Limit None Integrated  Abnormal Inductor Current Accumulation Can Be
Prohibited
 Increase System Reliability by Testing for Input
V IN-Absent Supply Voltage
None Integrated
Detection  Guarantee Stable Operation at Short Electric
Pow er Failure

Soft-Start and  Reduce Voltage and Current Stress at Startup

Startup w ithout None Integrated  Eliminate Audible Noise due to Unw anted OVP
Overshoot Triggering
 Can Avoid Burst Operation at Light Load and High
Control Range Input Voltage
None Integrated
Compensation  Reduce Probability of Audible Noise Due to Burst
Operation
THD Optimizer External Internal  No External Resistor Needed

140°C w ith  Stable and Reliable TSD Operation

TSD None
60°C Hysteresis  Converter Temperature Range Limited Range

Comparison of FAN7930C and FAN7930B

Function FAN7930C FAN7930B Remark
RDY Pin Integrated None
 User Choice for the Use of Number #2 Pin
OVP Pin None Integrated

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 FAN7930C — Critical Conduction Mode PFC Controller
Typical Performance Characteristics

Figure 4. Voltage Feedback Input Threshold 1 (V REF1) Figure 5. Start Threshold Voltage (V START) vs. T A
vs. T A

Figure 6. Stop Threshold Voltage (V STOP) vs. TA Figure 7. Startup Supply Current (ISTART) vs. T A

Figure 8. Operating Supply Current (I OP) vs. T A Figure 9. Output Upper Clam p Voltage (V EAH) vs. T A

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 FAN7930C — Critical Conduction Mode PFC Controller
Typical Performance Characteristics

Figure 10. Zero Duty Cycle Output Voltage (V EAZ) Figure 11. Maxim um On-Tim e Program 1 (t ON,MAX1)
vs. T A vs. T A

Figure 12. Maxim um On-Tim e Program 2 (t ON,MAX2) Figure 13. Current-Sense Input Threshold Voltage
vs. T A Lim it (V CS) vs. T A

Figure 14. Input High Clam p Voltage (V CLAMPH) vs. T A Figure 15. Input Low Clam p Voltage (V CLAMPL) vs. T A

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 FAN7930C — Critical Conduction Mode PFC Controller
Typical Performance Characteristics

Figure 16. Output Voltage High (V OH) vs. TA Figure 17. Output Voltage Low (V OL) vs. T A

Figure 18. Restart Tim er Delay (t RST) vs. TA Figure 19. Output Ready Voltage (V RDY) vs. T A

Figure 20. Output Saturation Voltage (V RDY,SAT) Figure 21. OVP Threshold Voltage (V OVP) vs. TA
vs. T A

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 FAN7930C — Critical Conduction Mode PFC Controller
Applications Information
VOUTPFC
1. Startup: Nor mally, supply voltage (V CC) of a PFC
block is fed from the additional pow er supply, w hich can +
2.240V/2.051V
UVLO
be called standby pow er. Without this standby pow er, -
disable

auxiliary w inding for zero current detection can be used -

2.675V/2.5V
as a supply source. Once the supply voltage of the PFC OVP 2.5 2.675

+
block exceeds 12 V, internal operation is enabled until disable

-
the voltage drops to 8. 5 V. If V CC exceeds V Z, 20 mA INV open 0.35 0.45

current is sinking from V CC. + 0.45V/0.35V

+
2.5V
PFC Inductor INV
VINPFC VOUTPFC high
-
1
2.051 2.240 disable
Aux. Winding 2 3
RDY COMP
VCC’

External VCC circuit

when no standby power exists
Figure 23. Circuit Around INV Pin
VOUTPFC
390Vdc 413V
390V
349V
VCC’ H:open VCC 320V
VREF 2.5VREF 8

Internal
- VZ
VBIAS Bias reset 70V
+ 55V
VTH(S/S) 20mA
VINV
8.5 2.65V
12 2.50V 2.50V
2.24V 2.051V

Figure 22. Startup Circuit 0.45V 0.35V

VCC

15V

2. INV Block: Scaled-dow n voltage from the output is

2.0V
the input for the INV pin. Many functions are embedded
IOUTCOMP
based on the INV pin: transconductance amplifier,
output OV P comparator, disable comparator, and output Current sourcing Current sourcing

UVLO comparator. Disable I sinking

For the output voltage contr ol, a transconductance

amplifier is used instead of the conventional voltage VRDY
amplifier. The transconductance amplifier (voltage- Voltage is decided by pull-up voltage.
controlled c urrent source) aids the implementation of
OVP
the OV P and disable functions. The output current of Vcc<2V, internal logic is not alive.
- RDY pin is floating, so pull up voltage is shown.
the amplifier changes according to the voltage - Internal signals are unknown.
t
difference of the inverting and non- inver ting input of
the amplifier. To cancel dow n the line input voltage Figure 24. Tim ing Chart for INV Block
effect on pow er factor correction, the effective contr ol
response of the PFC bloc k should be slow er than the
3. RDY Output: When the INV voltage is higher than
line frequency and this conflicts w ith the transient
2.24 V, RDY output is triggered HIGH and lasts until the
response of contr oller. Tw o-pole one-zer o type
INV voltage is low er than 2.051 V. When input AC
compensation can meet both requirements.
voltage is quite high, for example 240 V AC, PFC output
The OV P comparator shuts dow n the output drive block voltage is alw ays higher than RDY threshold, regardless
when the voltage of the INV pin is higher than 2.675 V of boost converter operation. In this case, the INV
and there is 0. 175 V hysteresis. The disable comparator voltage is already higher than 2.24 V before PFC V CC
disables operation w hen the voltage of the inverting input touches V START; how ever, RDY output is not triggered to
is low er than 0.35 V and there is 100 mV hysteresis. An HIGH until V CC touches V START. After boost converter
external small-signal MOSFET can be used to disable the operation stops, RDY is not pulled LOW because the
IC, as show n in Figure 23. The IC operating current INV voltage is higher than the RDY threshold. When V CC
decreases to reduce pow er consumption if the IC is of the PFC drops below 5 V, RDY is pulled LOW even
disabled. Figure 24 is the timing chart of the internal though PFC output voltage is higher than threshold. The
circuit near the INV pin w hen rated PFC output voltage RDY pin output is open drain, so needs an external pull-
is 390 V DC and V CC supply voltage is 15 V. up resistor to supply the proper pow er source. The RDY
pin output remains floating until V CC is higher than 2 V.

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 FAN7930C — Critical Conduction Mode PFC Controller
VCC 4. Control Range Com pensation: On time is controlled
by the output voltage compensator w ith FAN7930 C.
VSTART Due to this w hen input voltage is high and load is light,
VSTOP
control range becomes narrow compared to w hen input
5V PFC operation voltage is low . That control range decrease is inversely
proportional to the double square of the input voltage
VINV(=VPFCOUT) ( ). Thus at high line,
2.500V unw anted burst operation easily happens at light load
2.240V and audible noise may be generated from the boost
2.051V
inductor or inductor at input filter. Different from the
other converters, burst operation in PFC block is not
VRDY needed because the PFC block itself is nor mally
disabled dur ing standby mode. To reduce unw anted
burst operation at light load, an internal control range
t compensation function is implemented and show s no
VCC burst operation until 5% load at high line.

VSTART
5. Zero-Current Detection: Zero-current detection
VSTOP (ZCD) generates the turn-on signal of the MOSFET
5V PFC operation when the boost inductor current reaches zero using an
auxiliary w inding coupled w ith the inductor. When the
pow er sw itch turns on, negative voltage is induced at the
VINV(=VPFCOUT) auxiliary w inding due to the opposite w inding direction
2.500V (see Equation 1). Positive voltage is induced (see
2.240V Equation 2) w hen the pow er switch turns off.
2.051V
T
VAUX   AUX  VAC
TIND (1)
VRDY

VAUX  AUX  VPFCOUT  VAC 

T
(2)
t TIND
Figure 25. Tw o Cases of RDY Triggered HIGH w here:
VCC V AUX is the auxiliary w inding voltage;
TIND is boost inductor turns;
VSTART
TIND auxiliary w inding turns;
VSTOP
V AC is input voltage for PFC converter; and
5V PFC operation
V OUT_PFC is output voltage from the PFC converter.
PFC Inductor
VINPFC VOUTPFC
VINV(=VPFCOUT)
Aux Winding
2.500V
2.240V
2.051V VCC

RZCD
Negative Clamp
Circuit
VRDY
ZCD
5 -

CZCD +
t VTH(ZCD) Restart
Timer
Positive Clamp
VCC Circuit
optional fMAX gate
S Q limit driver
VSTART THD optimized
Sawtooth R Q
VSTOP Generator

5V PFC operation
Figure 27. Circuit Near ZCD
VINV(=VPFCOUT) Because aux iliary w inding voltage can sw ing from
negativ e to positive voltage, the inter nal bloc k in Z CD
2.500V
2.240V pin has both pos itiv e and negative voltage c lamping
2.051V
circuits. When the auxiliary voltage is negative, an
internal circuit clamps the negativ e voltage at the Z CD
pin ar ound 0.65 V by sourcing current to the serial
VRDY
resistor betw een the Z CD pin and the auxiliary
w inding. When the auxiliary voltage is higher than
t 6.5 V, current is sinked through a resistor from the
auxiliary w inding to the ZCD pin.
Figure 26. Tw o Cases of RDY Triggered LOW
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 FAN7930C — Critical Conduction Mode PFC Controller
ISW
VOUT
IMOSFET IDIODE VACIN VIN

VCC
VAUX & VZCD

VAUX tRESTART

VZCD 150 s

MOSFET gate
6.2V
0.65V

t ZCD after COMPARATOR

Figure 28. Auxiliary Voltage Depends on t

MOSFET Sw itching
Figure 30. Restart Tim er at Startup
The aux iliary w inding voltage is used to check the boost
Because the MOSFET turn-on depends on the Z CD
inductor current zero instance. When boost inductor
input, sw itching frequency may increase to higher than
current becomes zero, there is a resonance betw een
several megahertz due to the mis-triggering or noise on
boost inductor and all capacitors at the MOSFET drain
the nearby ZCD pin. If the sw itching frequency is higher
pin: inc luding COSS of the MOSFET; an external
than needed for critical conduction mode ( CRM),
capacitor at the D-S pin to reduce the voltage rising and
operation mode shifts to continuous conduction mode
falling slope of the MOSFET; a parasitic capacitor at
(CCM). In CCM, unlike CRM w here the boost inductor
inductor; and so on to improve performance. Resonated
current is reset to zero at the next sw itch on; inductor
voltage is reflected to the auxiliary w inding and can be
current builds up at every sw itching cycle and can be
used for detecting zero current of boost inductor and
raised to very high current that exceeds the current
valley position of MOSFET voltage stress. For valley
rating of the pow er sw itch or diode. This can seriously
detection, a minor delay by the resistor and capacitor is
damage the pow er sw itch. To avoid this, maximum
needed. A capacitor increases the noise immunity at the
sw itching frequency limitation is embedded. If ZCD
ZCD pin. If Z CD voltage is higher than 1.5 V, an internal
signal is applied again w ithin 3.3 μs after the previous
ZCD comparator output becomes HIGH and LOW w hen
rising edge of gate signal, this signal is ignored
the ZCD goes below 1.4 V. At the falling edge of
internally and FA N7930C w aits for another ZCD signal.
comparator output, internal logic turns on the MOSFET
This slightly degrades the pow er factor performance at
VDS light load and high input voltage.
ZCD after COMPARATOR Ignores ZCD noise
VOUTPFC - VIN

VOUTPFC - VIN
VIN
MOSFET Gate Error occurs!

IINDUCTOR
Max. fSW Limit

IMOSFET IDIODE
t
Inhibit Region

VZCD Figure 31. Maxim um Sw itching Frequency

Lim it Operation
6. Control: The scaled output is compared w ith the
1.5V
internal reference voltage and sinking or sourcing
1.4V current is generated from the COMP pin by the
transconductance amplifier. The error amplifier output is
MOSFET gate 150ns Delay compared w ith the internal saw tooth w aveform to give
proper turn-on time based on the controller.
ON ON

t
Figure 29. Auxiliary Voltage Threshold
When no Z CD signal is available, the PFC controller
cannot turn on the MOSFET, so the controller chec ks
every switching off time and forces MOSFET turn on
when the off time is longer than 150 μs. This restart
timer triggers MOSFET turn-on at startup and may be
used at the input voltage zero-cross period.

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 FAN7930C — Critical Conduction Mode PFC Controller
VOUTPFC For the transconductance error amplifier side, gain
changes based on differential input. When the error is
large, gain is large to suppress the output dip or peak
6.2V quickly. When the error is small, low gain is used to
THD-Optimized 1V improve pow er factor performance.
Sawtooth + MOSFET Off
Generator Sawtooth
- ICOMP
INV
1 -
VREF
Stair +
Powering
Step

250 mho
Clamp

Sourcing
Circuit
COMP

2.4V

2.5V

2.6V
3

R1
C2
C1
115 mho

Figure 32. Control Circuit

Unlike a conventional voltage- mode PWM controller,

Sinking
FA N7930C turns on the MOSFET at the falling edge of
ZCD signal. The “ ON” instant is deter mined by the
external signal and the turn-on time lasts until the error Braking
amplifier output (V COMP) and saw tooth w aveform meet.
When load is heavy, output voltage decreases, scaled Figure 35. Gain Characteristic
output decreases, COMP voltage increases to
7. Soft-Start: When V CC reaches V START, the internal
compensate low output, turn-on time lengthens to give
reference voltage is increased like a stair step for 5 ms.
more inductor turn-on time, and increased inductor
As a result, V COMP is also raised gradually and MOSFET
current raises the output voltage. This is how a PFC
turn-on time increases smoothly. This reduces voltage
negative feedback controller regulates output.
and current stress on the pow er sw itch during startup.
The maximum of V COMP is limited to 6. 5 V, w hich VCC
dictates the max imum turn-on time. Sw itching stops
w hen V COMP is low er than 1.0 V.
VSTART=12V
ZCD after COMPARATOR

VREFSS VREFEND=2.5V
VCOMP & Sawtooth
5ms

0.155 V / s
VINV=0.4V
MOSFET gate
gM

t
Figure 33. Turn-On Tim e Determ ination
The roles of PFC controller are regulating output voltage ISOURCECOMP (VREFSS-VINV) gM=ISOURCECOMP
and input current shaping to increase pow er factor. Duty
control based on the output voltage should be fast
enough to compensate output voltage dip or overshoot.
For the pow er factor, how ever, the control loop must not
react to the fluctuating A C input voltage. These tw o
VCOMP ISOURCECOMP RCOMP=VCOMP
requirements conflict; therefore, w hen designing a
feedback loop, the feedbac k loop should be least ten
times slow er than AC line frequency. That slow
response is made by C1 at the compensator. R1 makes
gain boost around operation region and C2 attenuates
t
gain at higher frequency. Boost gain by R1 helps raise
the response time and improves phase margin. Figure 36. Soft-Start Sequence
Gain 8. Startup w ithout Overshoot: Feedback control speed
Integrator of PFC is quite slow . Due to the slow response, ther e is
C1
Proportional
a gap betw een output voltage and feedback control.
gain That is w hy over-voltage protection ( OV P) is critical at
R1 the PFC controller and voltage dip caused by fast load
Freq. changes from light to heavy is diminished by a bulk
C2 capacitor. OV P is triggered dur ing startup phase.
High-Frequency Operation on and off by OV P at startup may cause
Noise Filter
audible noise and can increase voltage stress at startup,
Figure 34. Com pensators Gain Curve
[Link]
14
 FAN7930C — Critical Conduction Mode PFC Controller
which is nor mally higher than in nor mal operation. This
IIN
operation is improved w hen soft-start time is very long.
How ever, too much startup time enlarges the output
voltage building time at light load. FA N7930C has
overshoot protection at startup. During startup, the
feedback loop is controlled by an internal proportional IINDUCTOR
gain controller and, w hen the output voltage reaches the
rated value, it sw itches to an external compensator after
a transition time of 30 ms. This internal proportional gain IMOSFET IDIODE
controller eliminates overshoot at startup and an
VZCD INEGATIVE
external conventional compensator takes over
successfully afterw ard.
VOUT
Conventional Controller 1.5V
Startup Overshoot
1.4V

150ns
Startup Overshoot Control
MOSFET gate

ON ON
Control Transition t
Figure 38. Input and Output Current Near Input
VCOMP Voltage Peak
IIN
Depends on Load

Internal Controller IINDUCTOR

t VZCD
INEGATIVE
Figure 37. Startup w ithout Overshoot

9. T HD Optim ization: Total Har monic Distortion (THD) 1.5V

is the factor that dictates how closely input current 1.4V
shape matches sinusoidal form. The turn-on time of the
PFC controller is almost constant over one A C line 150ns
MOSFET gate
period due to the extremely low feedback control
response. The turn-off time is deter mined by the current
decrease slope of the boost inductor made by the input ON ON ON ON
voltage and output voltage. Once inductor current t
becomes zero, resonance betw een COSS and the boost
inductor makes oscillating w aveforms at the drain pin Figure 39. Input and Output Current Near Input
and auxiliary w inding. By checking the aux iliary w inding Voltage Peak Zero Cross
voltage through the Z CD pin, the controller can check To improve this, lengthened turn-on time near the zero
the zero current of boost inductor. At the same time , a cross region is a w ell-know n technique, though the
minor delay is inserted to deter mine the valley position method may vary and may be proprietary. FA N7930C
of drain voltage. The input and output voltage difference optimizes this by sourcing current through the Z CD pin.
is at its maximum at the zero cross point of AC input Auxiliary w inding voltage becomes negative w hen the
voltage. The current decrease slope is steep near the MOSFET turns on and is proportional to input voltage.
zero cross region and more negative inductor current The negative clamping circuit of ZCD outputs the
flow s during a drain voltage valley detection time. Such current to maintain the Z CD voltage at a fixed value.
a negative inductor current cancels dow n the positive The sourcing current from the Z CD is directly
current flow s and input current becomes zero, called proportional to the input voltage. Some portion of this
“zero-cross distortion” in PFC. current is applied to the internal saw tooth generator,
together w ith a fixed-current source. Theoretically, the
fixed-current source and the capacitor at saw tooth
generator deter mine the maximum turn-on time w hen no
current is sourcing at Z CD c lamp circuit and available
turn-on time gets shorter proportional to the Z CD
sourcing current.

[Link]
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 FAN7930C — Critical Conduction Mode PFC Controller
VOUT
VIN
VAUX

Though VIN is
RZCD eliminated, operation of
Vcc
controller is normal due
THD Optimizer to the large bypass
capacitor.

N
1
VAUX

ZCD
5
MOSFET gate fMIN DMAX
Zero-Current
Detect

VCOMP
VREF

IMOT

IDS High drain

current!
reset CMOT

Sawtooth Generator
t
Figure 42. Without V IN-Absent Circuit
Figure 40. Circuit of THD Optim izer
VOUT
tON is typically constant over 1 AC line frequency, VIN
but tON is changed by ZCD voltage.
VZCD
tON
Though VIN is
eliminated, operation of
controller is normal due
to the large bypass
capacitor.

tON not shorter t

VAUX
tON get shorter

VZCD at FET on
Figure 41. Effect of THD Optim izer
DMAX
By THD optimizer, turn-on time over one A C line per iod MOSFET gate fMIN
DMIN
fMIN
is proportionally changed, depending on input voltage.
Near zero cross, lengthened turn-on time improves THD
performance. NewVCOMP
VIN Absence Detected
10. V IN-Absent Detection: To save pow er loss caused
by input voltage sensing resistors and to optimize THD,
the FA N7930C omits AC input voltage detection.
Therefore, no information about AC input is available IDS
Smooth
from the internal controller. In many cases, the V CC of Soft-Start
PFC controller is supplied by an independent pow er
source, like standby pow er. In this scheme, some t
mis match may ex ist. For example, w hen the electric Figure 43. With V IN-Absent Circuit
pow er is suddenly interrupted during tw o or three AC
line per iods; V CC is still live dur ing that time, but output 11. Current Sense : The MOSFET current is sensed
voltage drops because there is no input pow er source. using an external sensing resistor for over-current
Consequently, the control loop tries to compensate for protection. If the CS pin voltage is higher than 0.8 V, the
the output voltage drop and V COMP reaches its over-current protection comparator generates a
maximum. This lasts until A C input voltage is live again. protection signal. An internal RC filter of 40 kΩ and 8 pF
When AC input voltage is live again, high V COMP allows is included to filter sw itching noise.
high sw itching current and more stress is put on the 12. Gate Driver Output: FAN7930C contains a single
MOSFET and diode. To protect against this, FA N7930C totem-pole output stage designed for a direct dr ive of
checks if the input A C voltage ex ists. If input does not the pow er MOSFET. The drive output is capable of up
exist, soft-start is reset and w aits until AC input is live to +500 / -800 mA peak current w ith a typical rise and
again. Soft-start manages the turn-on time for smooth fall time of 50 ns w ith 1 nF load. The output voltage is
operation w hen it detects AC input is applied again and clamped to 13 V to protect the MOSFET gate even if the
applies less voltage and current stress on startup. V CC voltage is higher than 13 V.
[Link]
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 FAN7930C — Critical Conduction Mode PFC Controller
PCB Layout Guide

PFC block nor mally handles high sw itching current and

the voltage low energy signal path can be affected by
the high energy path. Cautious PCB layout is mandatory
for stable operation.
1. The gate drive path should be as short as possible.
The closed-loop that starts from the gate driver,
MOSFET gate, and MOSFET source to ground of
PFC controller should be as close as possible. This
is also crossing point betw een pow er ground and
signal ground. Pow er ground path from the bridge
diode to the output bulk capacitor should be short
and w ide. The shar ing position betw een pow er
ground and signal ground should be only at one
position to avoid ground loop noise. Signal path of
the PFC controller should be short and w ide for
external components to contact.
2. The PFC output voltage sensing resistor is nor mally
high to reduce current consumption. This path can
be affected by external noise. To reduce noise
potential at the INV pin, a shorter path for output
sensing is recommended. If a shorter path is not
possible, place some dividing resistors betw een
PFC output and the INV pin — closer to the INV pin
is better. Relative high voltage close to the INV pin
can be helpful. Figure 44. Recom m ended PCB Layout
3. The Z CD path is recommended close to auxiliary
w inding from boost inductor and to the Z CD pin. If
that is difficult, place a s mall capac itor (below
50 pF) to reduce noise.
4. The sw itching current sense path should not share
w ith another path to avoid interference. Some
additional components may be needed to reduce
the noise level applied to the CS pin.
5. A stabilizing capacitor for VCC is recommended as
close as possible to the V CC and ground pins. If it is
difficult, place the SMD capacitor as c lose to the
corresponding pins as possible.

[Link]
17
 FAN7930C — Critical Conduction Mode PFC Controller
Typical Application Circuit

Application Device Input Voltage Rated Output Output Voltage

Range Power (Maximum Current)
LCD TV Pow er Supply FAN7930C 90-265 V AC 195 W 390 V (0.5 A)

Features
 Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 95% at universal input.
 Pow er factor at rated load is higher than 0.98 at universal input.
 Total Harmonic Distortion (THD) at rated load is low er than 15% at universal input.

Key Design Notes

 When auxiliary V CC supply is not available, V CC pow er can be supplied through Zero Current Detect (ZCD)
w inding. The pow er consumption of R103 is quite high, so its pow er rating needs checking.
 Because the input bias current of INV pin is almost zero, output voltage sensing resistors (R112~R115) should
be as high as possible. How ever, too-high resistance makes the node susceptible to noise. Resistor values need
to strike a balance betw een pow er consumption and noise immunity.
 Quick charge diode (D106) can be eliminated if output diode inrush current capability is sufficient. Even w ithout
D106, system operation is normal due to the controller’s highly reliable protection features.

Schematic
Optional
D106
600V 3A

D105
194µH, 39:5 600V 8A DC OUTPUT

LP101,EER3019N
C1030,68m

BD101,
F,630Vdc

R112
3.9M
600V,15A VAUX
R103,
R102,
330k

10k,1W

R113
3.9M
D101,1N474

C104, R109
12nF 47
6
R104,

D102, Q101
30k

UF4004 FCPF

R114
20N60 3.9M
TH101

220mF, 450V
,5D15

R108 D103,1N414
8 7 4.7 8
VCC Out

C111
C102,
680nF 5 ZCD
CS 4
3
Comp 1
2 INV
C105, 100nF

RDY
C107
,33m
,23mH
LF101

GND
0.08, 5W
F

D104,1N414

R111

R115
75k

6
R110,10k
R107 C108,
,10k 220nF

C112,470p

C114 C115
C110,1n

,2.2n ,2.2n
C109
,47n

F F
F

C101,
220nF
R101,1M-
J
VCC for another power stage

ZNR101
,10D471
FS101,
250V,5
A

Circuit for VCC. If external VCC is used, this circuit is not needed.

Circuit for VCC for another power stage thus components structure and values may vary.

Figure 45. Dem onstration Circuit

[Link]
18
 FAN7930C — Critical Conduction Mode PFC Controller
Transformer

EER3019N
9,10 1,2 Naux 9,10 6,7

1,2
Naux NP

6,7 3,4
Np

3,4

Figure 46. Transform er Schem atic Diagram

Winding Specification

Position No Pin (S → F) Wire Turns Winding Method

Np 3, 4 → 1, 2 0.1φ×50 39 Solenoid Winding

Bottom
Insulation: Polyester Tape t = 0.05mm, 3 Layers
NAUX 9,10 → 6,7 0.3φ 5 Solenoid Winding
Top
Insulation: Polyester Tape t = 0.05 mm, 4 Layers

Electrical Characteristics
Pin Specification Remark
Inductance 3, 4 → 1, 2 194 H ±5% 100 kHz, 1 V

Core & Bobbin

2
Core: EER3019, Samhw a (PL-7) (Ae=137.0mm )
Bobbin: EER3019

[Link]
19
 FAN7930C — Critical Conduction Mode PFC Controller
Bill of Materials
Part # Value Note Part # Value Note
Resistor Sw itch
R101 1 MΩ 1W Q101 FCPF20N60 20 A, 600 V, SuperFET®
R102 330 kΩ 1/2W Diode
R103 10 kΩ 1W D101 1N4746 1 W, 18 V, Zener Diode

R104 30 kΩ 1/4W D102 UF4004 1 A, 400 V Glass Passivated

High-Efficiency Rectifier
R107 10 kΩ 1/4W D103 1N4148 1 A, 100 V Small-Signal Diode
R108 4.7 kΩ 1/4W D104 1N4148 1 A, 100 V Small-Signal Diode

R109 47 kΩ 1/4W D105 8 A, 600 V, General-Purpose

Rectifier

R110 10 kΩ 1/4W D106 3 A, 600 V, General-Purpose

Rectifier
R111 0.80 kΩ 5W
R112,
3.9 kΩ 1/4W IC101 FAN7930C CRM PFC Controller
113, 114
R115 75 kΩ 1/4W
Capacitor Fuse
C101 220 nF / 275 V AC Box Capacitor FS101 5 A / 250 V
C102 680 nF / 275 V AC Box Capacitor NTC
C103 0.68 µF / 630 V Box Capacitor TH101 5D-15
C104 12 nF / 50 V Ceramic Capacitor Bridge Diode
C105 100 nF / 50 V SMD (1206) BD101 15 A, 600 V

C107 33 µF / 50 V Electrolytic Line Filter

Capacitor
C108 220 nF / 50 V Ceramic Capacitor LF101 23 mH
C109 47 nF / 50 V Ceramic Capacitor Transform er
2
C110 1 nF / 50 V Ceramic Capacitor T1 EER3019 Ae=137.0 mm
C112 47 nF / 50 V Ceramic Capacitor ZNR

C111 220 µF / 450 V Electrolytic ZNR101 10D471

Capacitor
C114 2.2 nF / 450 V Box Capacitor
C115 2.2 nF / 450 V Box Capacitor

[Link]
20
 FAN7930C — Critical Conduction Mode PFC Controller
Physical Dimensions

5.00 A
4.80 0.65
3.81
8 5
B

6.20 1.75
5.80 4.00 5.60
3.80

PIN ONE 1 4
INDICATOR
1.27
(0.33) 1.27
0.25 C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
1.75 MAX C 0.19
0.51 0.10
0.33 OPTION A - BEVEL EDGE

0.50 x 45°
0.25
R0.10 GAGE PLANE
OPTION B - NO BEVEL EDGE
R0.10 0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0° A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
0.90 SEATING PLANE B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
0.40 FLASH OR BURRS.
(1.04) D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
DETAIL A E) DRAWING FILENAME: M08Arev14
SCALE: 2:1
F) FAIRCHILD SEMICONDUCTOR.

Figure 47. 8-Lead, Sm all Outline Package (SOP)

Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in
any manner without notice. Please note the revision and /or date on the drawing and contact a ON Semiconductor representative to
verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms
and conditions, specifically the warranty therein, which covers ON Semiconductor products.

[Link]
21
 FAN7930C — Critical Conduction Mode PFC Controller
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