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International Journal of Advanced Research Trends in Engineering and Technology (IJARTET)
Vol. 5, Special Issue 11, April 2018
DESIGN OF FAST DADDA MULTIPLIER USING VEDIC MATHEMATICS
B.Shanmathi1 PG Scholar Dr.G.A.Sathishkumar2 professor
Department of ECE Department of ECE
Sri Venkateswara College of Engineering Sri Venkateswara College of Engineering
Sriperumbudhur-602117 Sriperumbudhur-602117
b.shanmathi1994@[Link] sathish@[Link]
Abstract— In VLSI design, the performance of any To increase the performance of the multiplier as well
system is based on the performance of the multiplier. But as for the high speed multiplication, Vedic mathematics is
multipliers are the most area and power consuming circuits. used. Vedic mathematics is a collection of sutras which
Improvement in any of these parameters increases the consists of 16 sutras and 13 sub sutras. These sutras are used
performance of the multiplier. This paper proposes the Dadda
to solve problems such as arithmetic, algebra, geometry,
multiplier, in which the partial product and adder stage are
performed using one of the sutras of the Vedic mathematics. This calculus. Indian mathematician Jagadguru Shri Bharathi
paper presents a Novel approach towards the reduction of delay Krishna Tirthaji discovered the Vedic mathematics. Veda is a
in Dadda multiplier by using Urdhva Triyakbhyam and the Sanskrit word which means Knowledge. Using regular
partial product addition in realized using Ripple Carry Adder. mathematical steps, solving problems sometimes leads to
The Vedic multiplier with Ripple carry adder has been designed more complex and power consuming. By using Vedic
using Verilog HDL and simulated in Xilinx ISE simulator 14.1 mathematics General Techniques and Specific Techniques,
and also synthesized using Cadence EDA tool. The Dadda numerical calculation can be done at very fast speed.
multiplier are compared with existing literature based on path
delay and the result shows that proposed Dadda multiplier with
A. Dadda multiplier
Vedic mathematics are faster with least path delay.
The scientist Luigi Dadda was designed the hardware
Keywords-Vedic mathematics, Dadda Multiplier, Delay, multiplier known as Dadda multiplier. The Dadda multiplier is
Power consumption, Urdhva Triyakbhyam identical to the Wallace multiplier, although it is little faster
and the number of gates required is also less compared to
Wallace tree multiplier. Both of these multipliers consist of
three stages. In the first stage, the product matrix is formed. In
I. INTRODUCTION the second stage, this product matrix is reduced to a height of
A multiplier is one of the major blocks in digital two rows. In the final stage, these two rows are combined
signal processing, ALU and other logic computations. The using an appropriate adder. Even though in the Wallace
speed of the processor determines its performance. High speed multiplier, the products are reduced as fast as possible. In
processing is the imperative requirement of all the systems. In contrast, Dadda multiplier does the minimum reduction
modern VLSI design, the trade of the high speed necessary at each level to perform the reduction of the product
multiplication is ever increasing. Multiplier is the essential in the same number of levels as required by a Wallace
component in digital signal processing application and thus multiplier. Generally it is considered that, both the multipliers
the speed of the circuit is based on the design of the multiplier. exhibit similar delay. Because to perform the partial product
Prior works some multipliers were considered as high speed reduction both the multiplier uses the same number of pseudo
multiplier example Booth multiplier, Modified Booth adder levels.
multiplier, Array multiplier etc. Although these multipliers
involves many intermediate steps, which reduces their speed B. Vedic Mathematics–Sutra
and consumes more power. The demand of the fast Vedic mathematics is the technique which can be
multiplication has given rise to the fast multiplier called used for performing multiplication operation with the benefit
Dadda multiplier . of several sutras. Urdhva Triyakbhyam (UT) is one of the 16
different sutras based on Vedic mathematical sutras for
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Vol. 5, Special Issue 11, April 2018
multiplication. The “Urdhva Triyakbhyam” is derived from
the Sanskrit name “Urdhva” means “Vertical” and
“Triyakbhyam” means “Crosswise”. By applying vertically
crosswise technique the generation of partial product and the
addition are performed in a single stage. Because of this
parallel operation of partial product generation and addition
the speed of the multiplier is increased. In this approach which
multiplies the digits vertically and crosswise and finally adds
them using adder. The advantage of this method is that the
partial products needed for the multiplication are already
generated and this leads to decrease in delay and power
consumption. The Vedic mathematics can be used to compute
binary numbers as well as decimal numbers. This method can
also be directly applied to trigonometry, spherical geometry,
calculus and applied mathematics of various kinds. The
different branches of engineering such as Convolution,
Cryptography and Digital Signal Processing are practiced
based on Vedic sutras.
C. Adder
Inside the Vedic sutra block to combine the partial
product Ripple Carry Adder is used. A Ripple Carry Adder is
a digital circuit which is used to produce the sum of two
numbers. It can be constructed by connecting the full adder in
series, with the carry output from each full adder stage can be
connected as the carry input to the next stage of full adder. In
the ripple carry adder, the output is known after the carry
generated from the previous stage. Thus the sum of the most
significant bit is only available after the carry signal has
rippled from the least significant bit through the adder stages.
[Link] Dadda multiplier with Vedic Sutra
II. FAST DADDA MULTIPLIER USING URDHVA
TRIYAKBHYAM
Dadda multiplier proposed a predetermined method
for matrix to reduce the number of stages to the minimum
matrix height. In the regular Dadda multiplier, the total delay
due to the product matrix generation, the product summation
stage and finally due to the final adder stage. Among all these
three stages, the product summation stage has maximum delay
compared to other two stages. In this proposed paper, the
maximum delay obtained in the product summation stage can
be reduced with the help of one of the Vedic sutras called
Urdhva Triyakbhyam. In the fast Dadda multiplier, the array
can be partitioned into two parts as part 0 and part 1 at the first
stage. At the next stage, the partial product and final adder
stage can be performed at the same stage with the help of
Vedic sutra. Because of the partial product and adder are
performed at the same stage reduce the delay to the minimum
compared to the regular Dadda multiplier. The adder used in
the Vedic sutra is Ripple Carry Adder. A Ripple Carry Adder
is a digital circuit which is used to produce the sum of two
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numbers. It can be constructed by connecting the full adder in
series, with the carry output from each full adder stage can be
connected as the carry input to the next stage of full adder.
III. RESULTS AND DISCUSSION
A. SIMULATION RESULT USING XILINX ISE
SIMULATOR
In this section the simulation result of the Fast Dadda
multiplier using Vedic is described as follows. Figure 2
represent the simulation result of 16-bit Dadda multiplier
using Vedic is given. Figure 3 represent the simulation result
of 32-bit Dadda multiplier using Vedic is given. Figure 4
represent the simulation result of 64-bit Dadda multiplier
using Vedic is given. Figure 5 represent the simulation result Figure.3. Simulation result for 32 bit Fast Dadda multiplier using Vedic
of 128-bit Dadda multiplier using Vedic .
Figure.2. Simulation result for 16 bit Fast Dadda multiplier using Vedic Figure.4. Simulation result for 64 bit Fast Dadda multiplier using Vedic
Figure.5. Simulation result for 128 bit Fast Dadda multiplier using Vedic
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B. SYNTHESIS REPORT USING CADENCE EDA TOOL
In this section the synthesis report for the Fast Dadda
multiplier is described as follows. Figure 6 represent the delay
report for the 16-bit Fast Dadda multiplier. Figure 7 represent
the power report for the 16-bit Fast Dadda multiplier. Figure 8
represent the delay report for the 32-bit Fast Dadda multiplier.
Figure 9 represent the power report for the 32-bit Fast Dadda
multiplier. Figure 10 represent the delay report for the 64-bit
Fast Dadda multiplier. Figure 11 represent the power report
for the 64-bit Fast Dadda multiplier. Figure 12 represent the
delay report for the 128-bit Fast Dadda multiplier. Figure 13
represent the power report for the 128-bit Fast Dadda
multiplier.
Figure.7: Power report for 16-bit Dadda multiplier using Vedic
Figure.6: Delay report for 16-bit Dadda multiplier using Vedic
Figure.8: Delay report for 32-bit Dadda multiplier using Vedic
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Figure.9: Power report for 32-bit Dadda multiplier using Vedic Figure.10: Delay report for 64-bit Dadda multiplier using Vedic
Figure.11: Power report for 64-bit Dadda multiplier using Vedic
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Figure.13: Power report for 128-bit Dadda multiplier using Vedic
Figure.12: Delay report for 128-bit Dadda multiplier using Vedic
IV. PERFORMANCE COMPARISON
A. DELAY SUMMARIZATION USING CADENCE EDA
TOOL
The maximum combinational path delay obtained for
the Dadda multiplier with Vedic sutra and without Vedic sutra
using Cadence EDA tool is summarized in Table 1 and their
respective comparison representation is shown in figure 14.
The proposed Dadda Multiplier is coded using Verilog HDL
and simulated using Xilinx ISE simulator 14.1. Synthesis has
been performed using Cadence EDA tool.
Table.1: Delay summarization using Cadence EDA tool
DELAY 16-bit 32-bit 64-bit 128-bit
Dadda
multiplier
with
Vedic 11400ps 20772.70ps 41268.20ps 81417.40ps
Dadda
multiplier
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Vol. 5, Special Issue 11, April 2018
without multiplier 340380.50 1764062.90 8200686.04 36529528.13
Vedic with Vedic nw nw nw Nw
20123.50ps 32569.30ps 53789.20ps 98472.90ps
Dadda
multiplier 575755 2418316.20 11926461.5 43485600.21
without nw nw nw Nw
Vedic
120000
100000
80000
Dadda multiplier
60000 with Vedic
Dadda multiplier
40000 without Vedic
20000
0
16 bit 32 bit 64 bit 128
bit
Figure.14: Delay comparison of Dadda multiplier with Vedic and without
Vedic
Figure.15: Power comparison of Dadda multiplier with Vedic and without
Vedic
B. POWER SUMMARIZATION USING CADENCE EDA
TOOL
The maximum power consumption for the Dadda
multiplier with Vedic sutra and without Vedic sutra using
Cadence EDA tool is summarized in Table 2 and their
respective comparison representation is shown in figure 15.
The proposed Dadda Multiplier is coded using Verilog HDL V. CONCLUSION
and simulated using Xilinx ISE simulator 14.1. Synthesis has A technique for the multiplication of 128 bit
been performed using Cadence EDA tool. operands with the help of Vedic sutra is described. The
Proposed Dadda multiplier is based on Urdhva Triyakbhyam
Table.2: Power summarization using Cadence EDA tool sutra of Vedic mathematics. This sutra makes the parallel
generation of partial product and removes unwanted
multiplication steps. In this proposed design, the maximum
DELAY 16-bit 32-bit 64-bit 128-bit delay obtained in the product summation stage can be reduced
Dadda
with the help of one of the Vedic sutras called Urdhva
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