MC74HC14A

Hex Schmitt−Trigger
Inverter
High−Performance Silicon−Gate CMOS
The MC74HC14A is identical in pinout to the LS14, LS04 and the
HC04. The device inputs are compatible with Standard CMOS [Link]
outputs; with pullup resistors, they are compatible with LSTTL
outputs. MARKING
The HC14A is useful to “square up” slow input rise and fall times. DIAGRAMS
Due to hysteresis voltage of the Schmitt trigger, the HC14A finds 14
applications in noisy environments. PDIP−14
N SUFFIX MC74HC14AN
CASE 646 AWLYYWW
Features
• Pb−Free Packages are Available*
1
14
• Output Drive Capability: 10 LSTTL Loads SOIC−14
• Outputs Directly Interface to CMOS, NMOS and TTL D SUFFIX
HC14A
AWLYWW
• Operating Voltage Range: 2.0 to 6.0 V
CASE 751A

•
1
Low Input Current: 1.0
A 14
• High Noise Immunity Characteristic of CMOS Devices
HC
TSSOP−14
• In Compliance With the JEDEC Standard No. 7.0 A Requirements DT SUFFIX 14A
• Chip Complexity: 60 FETs or 15 Equivalent Gates CASE 948G ALYW

LOGIC DIAGRAM 1

1 2 A = Assembly Location
A1 Y1
WL or L = Wafer Lot
YY or Y = Year
3 4 WW or W = Work Week
A2 Y2

5 6 FUNCTION TABLE
A3 Y3
Inputs Outputs
Y=A
9 8 A Y
A4 Y4 Pin 14 = VCC
Pin 7 = GND L H
H L
11 10
A5 Y5

13 12
A6 Y6 ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Pinout: 14−Lead Packages (Top View)
VCC A6 Y6 A5 Y5 A4 Y4
14 13 12 11 10 9 8 *For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

1 2 3 4 5 6 7
A1 Y1 A2 Y2 A3 Y3 GND

 Semiconductor Components Industries, LLC, 2004 1 Publication Order Number:

December, 2004 − Rev. 9 MC74HC14A/D
 MC74HC14A

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MAXIMUM RATINGS

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Symbol
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Parameter Value Unit This device contains protection

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VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

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Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

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be taken to avoid applications of any
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
voltage higher than maximum rated

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Iin DC Input Current, per Pin ± 20 mA voltages to this high−impedance cir-

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cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA
Vout should be constrained to the

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ICC DC Supply Current, VCC and GND Pins ± 50 mA range GND
(Vin or Vout)
VCC.

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Unused inputs must always be
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

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SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450

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Unused outputs must be left open.
Tstg Storage Temperature Range – 65 to + 150
C

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TL
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Lead Temperature, 1 mm from Case for 10 Seconds

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Plastic DIP, SOIC or TSSOP Package 260

C

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Maximum ratings are those values beyond which device damage can occur. Maximum ratings

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applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

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damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/
C from 65
to 125
C
SOIC Package: – 7 mW/
C from 65
to 125
C
TSSOP Package: − 6.1 mW/
C from 65
to 125
C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

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RECOMMENDED OPERATING CONDITIONS

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Symbol Parameter Min Max Unit

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VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

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Vin, Vout DC Input Voltage, Output Voltage (Referenced to 0 VCC V
GND)

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TA
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Operating Temperature Range, All Package Types – 55 + 125
C

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tr, tf
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Input Rise/Fall Time

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(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
0
0
No Limit*
No Limit*
ns

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VCC = 6.0 V 0 No Limit*
*When Vin = 50% VCC, ICC > 1mA

ORDERING INFORMATION
Device Package Shipping†
MC74HC14AN PDIP−14 2000 Units / Box
MC74HC14ANG PDIP−14 2000 Units / Box
(Pb−Free)

MC74HC14AD SOIC−14 55 Units / Rail

MC74HC14ADG SOIC−14 55 Units / Rail
(Pb−Free)

MC74HC14ADR2 SOIC−14 2500 Units / Reel

MC74HC14ADR2G SOIC−14 2500 Units / Reel
(Pb−Free)

MC74HC14ADT TSSOP−14* 96 Units / Rail

MC74HC14ADTR2 TSSOP−14* 2500 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.

[Link]
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 MC74HC14A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V −55 to 25°C ≤85°C ≤125°C Unit
VT+ max Maximum Positive−Going Input Vout = 0.1V 2.0 1.50 1.50 1.50 V
Threshold Voltage |Iout| ≤ 20
A 3.0 2.15 2.15 2.15
(Figure 3) 4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VT+ min Minimum Positive−Going Input Vout = 0.1V 2.0 1.0 0.95 0.95 V
Threshold Voltage |Iout| ≤ 20
A 3.0 1.5 1.45 1.45
(Figure 3) 4.5 2.3 2.25 2.25
6.0 3.0 2.95 2.95
VT− max Maximum Negative−Going Input Vout = VCC − 0.1V 2.0 0.9 0.95 0.95 V
Threshold Voltage |Iout| ≤ 20
A 3.0 1.4 1.45 1.45
(Figure 3) 4.5 2.0 2.05 2.05
6.0 2.6 2.65 2.65
VT− min Minimum Negative−Going Input Vout = VCC − 0.1V 2.0 0.3 0.3 0.3 V
Threshold Voltage |Iout| ≤ 20
A 3.0 0.5 0.5 0.5
(Figure 3) 4.5 0.9 0.9 0.9
6.0 1.2 1.2 1.2
VHmax Maximum Hysteresis Voltage Vout = 0.1V or VCC − 0.1V 2.0 1.20 1.20 1.20 V
Note 2 (Figure 3) |Iout| ≤ 20
A 3.0 1.65 1.65 1.65
4.5 2.25 2.25 2.25
6.0 3.00 3.00 3.00
VHmin Minimum Hysteresis Voltage Vout = 0.1V or VCC − 0.1V 2.0 0.20 0.20 0.20 V
Note 2 (Figure 3) |Iout| ≤ 20
A 3.0 0.25 0.25 0.25
4.5 0.40 0.40 0.40
6.0 0.50 0.50 0.50
VOH Minimum High−Level Output Vin ≤ VT− min 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20
A 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin ≤ VT− min |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low−Level Output Vin ≥ VT+ max 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20
A 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin ≥ VT+ max |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0
A
Current
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 1.0 10 40
A
Current (per Package) Iout = 0
A
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
2. VHmin > (VT+ min) − (VT− max); VHmax = (VT+ max) − (VT− min).

[Link]
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 MC74HC14A

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

Guaranteed Limit
VCC
Symbol Parameter V −55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A or B to Output Y 2.0 75 95 110 ns
tPHL (Figures 1 and 2) 3.0 30 40 55
4.5 15 19 22
6.0 13 16 19
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 2) 3.0 27 32 36
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Inverter)* 22 pF

* Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).

tf tr
VCC
90%
INPUT A 50%
10% GND
tPLH tPHL

90%
OUTPUT Y 50%
10%

tTLH tTHL

Figure 1. Switching Waveforms

TEST
POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

[Link]
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 MC74HC14A

VT , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS

4

3
(VT+) VHtyp

2
(VT−)

2 3 4 5 6
VCC, POWER SUPPLY VOLTAGE (VOLTS)

VHtyp = (VT+ typ) − (VT− typ)

Figure 3. Typical Input Threshold, VT+, VT− versus Power Supply Voltage

A Y

(a) A Schmitt−Trigger Squares Up Inputs With Slow Rise and Fall Times (b) A Schmitt−Trigger Offers Maximum Noise Immunity

VCC VCC
VH VH
VT+ VT+
Vin Vin
VT− VT−

GND GND

VOH VOH

Vout Vout

VOL VOL

Figure 4. Typical Schmitt−Trigger Applications

[Link]
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 MC74HC14A

PACKAGE DIMENSIONS

PDIP−14
N SUFFIX
CASE 646−06
ISSUE N

NOTES:
1. DIMENSIONING AND TOLERANCING
14 8 PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B 3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
1 7 4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
INCHES MILLIMETERS
F L DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
N C
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
−T− G 0.100 BSC 2.54 BSC
SEATING H 0.052 0.095 1.32 2.41
PLANE J 0.008 0.015 0.20 0.38
K J K 0.115 0.135 2.92 3.43
H G D 14 PL M L 0.290 0.310 7.37 7.87
M −−− 10
−−− 10

0.13 (0.005) M
N 0.015 0.039 0.38 1.01

SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G

−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER
14 8 ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−B− 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
P 7 PL PER SIDE.
0.25 (0.010) M B M 5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
1 7 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
G R X 45
F CONDITION.
C
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
−T− B 3.80 4.00 0.150 0.157
K M J C 1.35 1.75 0.054 0.068
SEATING D 14 PL D 0.35 0.49 0.014 0.019
PLANE
0.25 (0.010) M T B S A S F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0
7
0
7

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

[Link]
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 MC74HC14A

PACKAGE DIMENSIONS

TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE O

NOTES:
14X K REF 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
0.10 (0.004) M T U S V S
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
N (0.006) PER SIDE.
0.25 (0.010) 4. DIMENSION B DOES NOT INCLUDE INTERLEAD
14 8
2X L/2 FLASH OR PROTRUSION. INTERLEAD FLASH OR
M PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
L PROTRUSION. ALLOWABLE DAMBAR
PIN 1
−U− N PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
IDENT. F EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1 7 6. TERMINAL NUMBERS ARE SHOWN FOR
DETAIL E REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
0.15 (0.006) T U S
A K MILLIMETERS INCHES

ÇÇÇ
ÉÉ
K1 DIM MIN MAX MIN MAX
−V− A 4.90 5.10 0.193 0.200

ÇÇÇ
ÉÉ
B 4.30 4.50 0.169 0.177
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
0.10 (0.004) M 0
8
0
8

−T− SEATING D G H DETAIL E
PLANE

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