VHDL has a rich and interesting history1

But since knowing this history

is probably not going to help you write better VHDL code, it will only be

briefly mentioned here. Consulting other, lengthier texts or search engines

will provide more information for those who are interested. Regarding

the VHDL acronym, the V is short for yet another acronym: VHSIC

or Very High-Speed Integrated Circuit. The HDL stands for Hardware

Description Language. Clearly, the state of technical affairs these days has

done away with the need for nested acronyms. VHDL is a true computer

language with the accompanying set of syntax and usage rules. But, as

opposed to higher-level computer languages, VHDL is primarily used to

describe hardware. The tendency for most people familiar with a higher level computer language such
as C or Java is to view VHDL as just another

computer language. This is not altogether a bad approach if such a view

facilitates the understanding and memorization of the language syntax and

structure. The common mistake made by someone with this approach is

to attempt to program in VHDL as they would program a higher-level

computer language. Higher-level computer languages are sequential in

nature; VHDL is not

VHDL was invented to describe hardware and in fact VHDL is a con current language. What this means
is that, normally, VHDL instructions

are all executed at the same time (concurrently), regardless of the size of

your implementation. Another way of looking at this is that higher-level

computer languages are used to describe algorithms (sequential execution)

and VHDL is used to describe hardware (parallel execution). This inherent

difference should necessarily encourage you to re-think how you write your

VHDL code. Attempts to write VHDL code with a high-level language

style generally result in code that nobody understands. Moreover, the

tools used to synthesize2

this type of code have a tendency to generate

circuits that generally do not work correctly and have bugs that are nearly

impossible to trace. And if the circuit does actually work, it will most likely

be inefficient due to the fact that the resulting hardware was unnecessarily

large and overly complex. This problem is compounded as the size and

complexity of your circuits becomes greater.

There are two primary purposes for hardware description languages such

as VHDL. First, VHDL can be used to model digital circuits and systems.

Although the word “model” is one of those overly used words in engineering,

in this context it simply refers to a description of something that presents

a certain level of detail. The nice thing about VHDL is that the level

of detail is unambiguous due to the rich syntax rules associated with it.

In other words, VHDL provides everything that is necessary in order to

describe any digital circuit. Likewise, a digital circuit/system is any circuit

that processes or stores digital information. Second, having some type of

circuit model allows for the subsequent simulation and/or testing of the

circuit. The VHDL model can also be translated into a form that can be

used to generate actual working circuits. The VHDL model is magically3

interpreted by software tools in such a way as to create actual digital

circuits in a process known as synthesis.

There are other logic languages available to model the behavior of digital

circuit designs that are easy to use because they provide a graphical

method to model circuits. For them, the tendency is to prefer the graphical

approach because it has such a comfortable learning curve. But, as you can

easily imagine, your growing knowledge of digital concepts is accompanied

by the ever-increasing complexity of digital circuits you are dealing with.

The act of graphically connecting a bunch of lines on the computer screen

quickly becomes tedious. The more intelligent approach to digital circuit

design is to start with a system that is able to describe exactly how your
digital circuit works (in other words, modeling it) without having to worry

about the details of connecting large quantities of signal lines. Having a

working knowledge of VHDL will provide you with the tools to model

digital circuits in a much more intelligent manner.

Finally, you will be able to use your VHDL code to create actual func tioning circuits. This allows you to
implement relatively complex circuits

in a relatively short period of time. The design methodology you will be

using allows you to dedicate more time to designing your circuits and less

time “constructing” them. The days of placing, wiring and troubleshooting

multiple integrated circuits on a proto-board are gone.

VHDL is a very exciting language that can allow the design and imple mentation of functions capable of
processing an enormous amount of data

by employing a relatively low-cost and low-power hardware. Moreover,

what is really impressive is that, via simple VHDL modules, you can

have direct access to basic ns-level logic events as well as communicate

using a USB port or drive a VGA monitor to visualize graphics of modest

complexity

Modeling digital circuits with VHDL is a form of modern digital design

distinct from schematic-based approaches. The programmer writes a loose

description of what the final logic circuit should do and a language compiler,

in this case called a synthesizer, attempts to “infer” what the actual final

physical logic circuit should be. Novice programmers are not always able to

convince the synthesizer to implement something that seems very clear in

their minds. A somehow old-fashioned alternative to a descriptive language

such as VHDL is one in which the programmer simply interconnects a

finite number of digital blocks that he has pooled from a library in an

attempt to reach the same objective. This approach is not only very time

consuming but also inherently limiting and very error prone.

Modern digital design is more about appropriately modeling digital

circuits and maintaining a quality description of the circuit. All that is left

now is to learn how to properly use VHDL to describe what you want to

implement.

Golden Rules of VHDL

Before you start, here are a couple of points that you should never forget

when working with VHDL.

VHDL is a hardware-design language. Although most people have

probably already been exposed to some type of higher-level computer

language, these skills are only indirectly applicable to VHDL. When you

are working with VHDL, you are not programming, you are “designing

hardware”. Your VHDL code should reflect this fact. What does this mean?

It means that unless you are inside certain constructs, your code lines will

be executed almost all at once. If your VHDL code appears too similar to

code of a higher-level computer language, it is probably bad VHDL code.

This is vitally important.

Have a general concept of what your hardware should look like.

Although VHDL is vastly powerful, if you do not understand basic digital

constructs, you will probably be unable to generate efficient digital circuits.

Digital design is similar to higher-level language programming in that even

the most complicated programming at any level can be broken down into

some simple programming constructs. There is a strong analogy to digital

design in that even the most complicated digital circuits can be described

in terms of basic digital constructs. In other words, if you are not able to

roughly envision the digital circuit you are trying to model in terms of

basic digital circuits, you will probably misuse VHDL, thus angering the

VHDL gods. VHDL is cool, but it is not as magical as it initially appears

to be.

Tools Needed for VHDL Development

VHDL is a language used to implement hardware which will run other

software (for example C). A Field Programmable Gate Array (FPGA)

is probably the most common device that you can use for your VHDL

implementations. If you want to do VHDL coding for FPGAs you will have

to play within the rules that current major FPGA manufacturers have

drawn up to help you (rules which also ensure their continued existence in

the market).

The successful implementation of a VHDL-based system roughly calls

for the following steps: VHDL code writing, compiling, simulation and

synthesis. All major FPGA manufacturers have a set of software and

hardware tools that you can use to perform the mentioned steps. Most of

these software tools are free of charge but are not open-source. Nevertheless,

the same tools follow a license scheme, whereby paying a certain amount

of money allows you to take advantage of sophisticated software features

or get your hands on proprietary libraries with lots of components (e.g. a

32-bit processor) that you can easily include in your own project.

If your have no interest in proprietary libraries you can use open-source

solutions (e.g. GHDL4 or BOOT5

) which will allow you to compile and

simulate your VHDL code using the open-source tool gcc6

. At the time

of writing, no open-source solution is available for the synthesis process.

However synthesis can be accomplished using a free-license version of any

major FPGA manufacturer’s software tool (e.g. Xilinx Vivado).

Thanks to the open-source community, you can write, compile and

simulate VHDL systems using excellent open-source solutions. This book

will show you how to get up and running with the VHDL language. For

further tasks such as synthesis and upload of your code into an FPGA, the

free of charge Xilinx Vivado7 or the Altera equivalent tool Quartus, can

be employed.
There are several features of VHDL that you should know before moving

forward. Although it is rarely a good idea for people to memorize anything,

you should memorize the basic concepts presented in this section. This

should help eliminate some of the drudgery involved in learning a new

programming language and lay the foundation that will enable you to

create visually pleasing and good VHDL source code.

2.1 Case Sensitivity

VHDL is not case sensitive. This means that the two statements shown

in Listing 2.1 have the exact same meaning (don’t worry about what the

statement actually means though). Keep in mind that Listing 2.1 shows an

example of VHDL case sensitivity and not good VHDL coding practices.

2.2 White Space

VHDL is not sensitive to white space (spaces and tabs) in the source

document. The two statements in Listing 2.2 have the exact same meaning.

Once again, Listing 2.2 is not an example of good VHDL coding style.

Note that Listing 2.2 once again indicates that VHDL is not case sensitive.

2.3 Comments

Comments in VHDL begin with the symbol “--” (two consecutive dashes).

The VHDL synthesizer ignores anything after the two dashes and up to

the end of the line in which the dashes appear. Listing 2.3 shows two types

of commenting styles. Unfortunately, there are no block-style comments

(comments that span multiple lines but do not require comment marks on

every line) available in VHDL.

Appropriate use of comments increases both the readability and the

understandability of VHDL code. The general rule is to comment any

line or section of code that may not be clear to a reader of your code

besides yourself. The only inappropriate use of a comment is to state

something that is patently obvious. It is hard to imagine code that has

too few comments so don’t be shy: use lots of comments. Research has
shown that using lots of appropriate comments is actually a sign of high

intelligence.

2.4 Parentheses

VHDL is relatively lax on its requirement for using parentheses. Like other

computer languages, there are a few precedence rules associated with the

various operators in the VHDL language. Though it is possible to learn

all these rules and write clever VHDL source code that will ensure the

readers of your code are left scratching their heads, a better idea is to

practice liberal use of parentheses to ensure the human reader of your

source code understands the purpose of the code. Once again, the two

statements appearing in Listing 2.4 have the same meaning. Note that

extra white space has been added along with the parentheses to make the

lower statement clearer

2.5 VHDL Statements

Similar to other algorithmic computer languages, every VHDL statement

is terminated with a semicolon. This fact helps when attempting to re move compiling errors from your
code since semicolons are often omitted

during initial coding. The main challenge then is to know what constitutes

a VHDL statement in order to know when to include semicolons. The

VHDL synthesizer is not as forgiving as other languages when superfluous

semicolons are placed in the source code.

2.6 if, case and loop Statements

As you will soon find out, the VHDL language contains if, case and

loop statements. A common source of frustration that occurs when learn ing VHDL are the classic
mistakes involving these statements. Always

remember the rules stated below when writing or debugging your VHDL

code and you will save yourself a lot of time. Make a note of this section as

one you may want to read again once you have had a formal introduction

to these particular statements.

ˆ Every if statement has a corresponding then component

ˆ Each if statement is terminated with an end if;

ˆ If you need to use an else if construct, the VHDL version is elsif

ˆ Each case statement is terminated with an end case;

ˆ Each loop statement has a corresponding end loop; statement

In general, you should not worry too much about memorizing code syntax

as chances are you will use an editor sophisticated enough to have code

snippets (namely Gedit1

). A good programmer distinguishes himself by

other means than perfectly remembering code syntax.

2.7 Identifiers

An identifier refers to the name given to various items in VHDL. Examples

of identifiers in higher-level languages include variable names and function

names. Examples of identifiers in VHDL include variable names, signal

names and port names (all of which will be discussed soon). Listed below

are the hard and soft rules (i.e. you must follow them or you should follow

them), regarding VHDL identifiers.

ˆ Identifiers should be self-describing. In other words, the text you apply

to identifiers should provide information as to the use and purpose of

the item the identifier represents.

ˆ Identifiers can be as long as you want (contain many characters). Shorter

names make for better reading code, but longer names present more

information. It is up to the programmer to choose a reasonable identifier

length.

ˆ Identifiers can only contain a combination of letters (A-Z and a-z),

digits (0-9) and the underscore character (“ ”).

ˆ Identifiers must start with an alphabetic character.

ˆ Identifiers must not end with an underscore and must never have two

consecutive underscores.
ˆ The best identifier for a function that calculates the position of the Earth

is CalcEarthPosition or calc earth position. Try to be consistent.

ˆ The best identifier for a variable that stores the age of your car is

AgeMyCar or age my car. Again, try to be consistent.

Remember, intelligent choices for identifiers make your VHDL code more

readable, understandable and more impressive to coworkers, superiors,

family and friends. A few examples of both good and bad choices for

identifier names appear in Listing 2.5 and in Listing 2.6.

2.8 Reserved Words

There is a list of words that have been assigned special meaning by the

VHDL language. These special words, usually referred to as reserved words,

cannot be used as identifiers when writing VHDL code. A partial list of

reserved words that you may be inclined to use appears in Listing 2.7. A

complete list of reserved words appears in the Appendix. Notably missing

from Listing 2.7 are standard operator names such as AND, OR, XOR,

2.9 VHDL Coding Style

Coding style refers to the appearance of the VHDL source code. Obviously,

the freedom provided by case insensitivity, indifference to white space

and lax rules on parentheses creates a coding anarchy. The emphasis in

coding style is therefore placed on readability. Unfortunately, the level

of readability of any document, particularly coding text, is subjective.

Writing VHDL code is similar to writing code in other computer languages

such as C and Java where you have the ability to make the document more

readable without changing the functioning of the code. This is primarily

done by indenting certain portions of the program, using self-describing

identifiers and providing proper comments when and where necessary.

Instead of stating here a bunch of rules for you to follow as to how your

code should look, you should instead strive to simply make your source

code readable. Listed below are a few thoughts on what makes readable
source code.

ˆ Chances are that if your VHDL source code is readable to you, it will

be readable to others who may need to peruse your document. These

other people may include someone who is helping you get the code

working properly, someone who is assigning a grade to your code, or

someone who signs your paycheck at the end of the day. These are

the people you want to please. These people are probably very busy

and more than willing to make a superficial glance at your code. Nice

looking code will slant such subjectivity in your favor.

ˆ If in doubt, your VHDL source code should be modeled after some

other VHDL document that you find organized and readable. Any code

you look at that is written down somewhere is most likely written by

someone with more VHDL experience than a beginner such as yourself.

Emulate the good parts of their style while on the path to creating an

even more readable style.

ˆ Adopting a good coding style helps you write code without mistakes.

As with other compilers you have experience with, you will find that

the VHDL compiler does a great job of knowing a document has an

error but a marginal job at telling you where or what the error is.

Using a consistent coding style enables you to find errors both before

compilation and after the compiler has found an error.

ˆ A properly formatted document explicitly presents information about

your design that would not otherwise be readily apparent.

This is par ticularly true when using proper indentation and sufficient comments

The “black-box” approach to any type of design implies a hierarchical

structure in which varying amounts of detail are available at each of the

different levels of the hierarchy. In the black-box approach, units of action

which share a similar purpose are grouped together and abstracted to a

higher level. Once this is done, the module is referred to by its inherently
more simple black-box representation rather than by the details of the

circuitry that actually performs that functionality. This approach has two

main advantages. First, it simplifies the design from a systems standpoint.

Examining a circuit diagram containing appropriately named black boxes is

much more understandable than staring at a circuit containing a countless

number of logic gates. Second, the black-box approach allows for the reuse

of previously written code.

Not surprisingly, VHDL descriptions of circuits are based on the black box approach. The two main parts
of any hierarchical design are the black

box and the stuff that goes in the black box (which can of course be other

black boxes). In VHDL, the black box is referred to as entity and the

stuff that goes inside it is referred to as the architecture. For this reason,

the VHDL entity and architecture are closely related. As you can probably

imagine, creating the entity is relatively simple while a good portion of

the VHDL coding time is spent on properly writing the architecture. Our

approach here is to present an introduction to writing VHDL code by

describing the entity and then moving on to the details of writing the

architecture. Familiarity with the entity will hopefully aid in your learning

of the techniques to describe the architecture.

3.1 Entity

The VHDL entity construct provides a method to abstract the functionality

of a circuit description to a higher level. It provides a simple wrapper for the

lower-level circuitry. This wrapper effectively describes how the black box

interfaces with the outside world. Since VHDL describes digital circuits, the

entity simply lists the various inputs and outputs of the underlying circuitry.

In VHDL terms, the black box is described by an entity declaration. The

syntax of the entity declaration is shown in Listing 3.1

my entity defines the name of the entity. The next section is nothing

more than the list of signals from the underlying circuit that are available
to the outside world, which is why it is often referred to as an interface

specification. The port name x is an identifier used to differentiate the

various signals. The next keyword (the keyword in) specifies the direction

of the signal relative to the entity where signals can either enter, exit or do

both. These input and output signals are associated with the keywords in,

out and inout1

respectively. The next keyword (the keyword std logic)

refers to the type of data that the port will handle. There are several data

types available in VHDL but we will primarily deal with the std logic

type and derived versions. More information regarding the various VHDL

data types will be discussed later.

When you attempt to write fairly complicated VHDL code, you will need

to split your code into different files, functions and packages constructors

which will help you better deal with your code. In this scenario, the entity

body will not only host the port definition statements but, most likely,

other procedures as well. We will talk about this later in the book.

Listing 3.2 shows an example of a black box and the VHDL code used to

describe it. Listed below are a few points to note about the code in List ing 3.2. Most of the points deal
with the readability and understandability

of the VHDL code.

ˆ Each port name is unique and has an associated mode and data type.

This is a requirement.

ˆ The VHDL compiler allows several port names to be included on a

single line. Port names are separated by commas. Always strive for

readability.

ˆ Port names are somewhat lined up in a feeble attempt to increase

readability. This is not a requirement but you should always be striving

for readability. Remember that white spaces are ignored by the compiler.

ˆ A comment, which tells us what this entity does, is included.

ˆ A black-box diagram of the circuit is also provided. Once again, drawing

some type of diagram helps with any VHDL code that you may be

writing. Remember: do not be scared, draw a picture.

Hopefully, you are not finding these entity specifications too challenging.

In fact, they are so straightforward, we will throw in one last twist before

we leave the realm of VHDL entities. Most of the more meaningful circuits

that you will be designing, analyzing and testing have many similar and

closely related inputs and outputs. These are commonly referred to as “bus

signals” in computer lingo. Bus lines are made of more than one signal

that differ in name by only a numeric character. In other words, each

separate signal in the bus name contains the bus name plus a number to

separate it from other signals in the bus. Individual bus signals are referred

to as elements of the bus. As you would imagine, buses are often used

in digital circuits. Unfortunately, the word bus also refers to established

data transfer protocols. To disambiguate the word bus, we will be using

the word “bundle” to refer to a set of similar signals and bus to refer to a

protocol.

Bundles are easily described in the VHDL entity. All that is needed is a

new data type and a special notation to indicate when a signal is a bundle

or not. A few examples are shown in Listing 3.3. In these examples note that

the mode remains the same but the type has changed. The std logic

data type has now been replaced by the word std logic vector to

indicate that each signal name contains more than one signal. There are

ways to reference individual members of each bundle, but we will get to

those details later.

As you can see by examining Listing 3.3, there are two possible methods

to describe the signals in a bundle. These two methods are shown in the

argument lists that follow the data type declaration. The signals in the

bundle can be listed in one of two orders which are specified by the to and
downto keywords. If you want the most significant bit of your bundle to

be the first bit on the left you use the downto keyword. Be sure not to

forget the orientation of signals when you are using this notation in your

VHDL model.

In the black box of Listing 3.3 you can see the formal notation for a bundle.

Note that the black box uses a slash-and-number notation. The slash across

the signal line indicates the signal is a bundle and the associated number

specifies the number of signals in the bundle. Worthy of mention regarding

the black box relative to Listing 3.3 is that the input lines sel1 and sel0

could have been made into one bundle containing the two signals

The data type std logic and the data type std logic vector is

what the IEEE has standardized for the representation of digital signals.

Normally, you should consider that these data types assume the logic value 1

or the logic value 0. However, as specified in the std logic 1164 package,

the implementation of the std logic type (and the std logic vector

type) is a little more generous and includes 9 different values, specifically:

0,1,U,X,Z,W,L,H,-.

The data type std logic becomes available to you soon after the dec laration library IEEE; use IEEE.std
logic 1164.all; at the

beginning of your code.

The reason for all these values is the desire for modeling three-state

drivers, pull-up and pull-down outputs, high impedance state and a few

others types of inputs/outputs. For more details refer to the IEEE 1164

Standard2.

Alternatively to the std logic data type, VHDL programmers some times use the much simpler data type
bit which has only the logic values

1 and 0.

3.2 VHDL Standard Libraries

The VHDL language as many other computer languages, has gone through
a long and intense evolution. Among the most important standardization

steps we can mention are the release of the IEEE Standard 1164 pack age as well as some child
standards that further extended the functionality

of the language. In order to take advantage of the main implementable

feature of VHDL you just need to import the two main library packages

as shown in lines 2∼4 of Listing 3.4

Once these packages have been included, you will have access to a very

large set of goodies: several data types, overloaded operators, various

conversion functions, math functions and so on. For instance, the inclusion

of the package numeric std.all will give you the possibility of using the

unsigned data type and the function to unsigned shown in Listing 3.4.

For a detailed description of what these libraries include, refer to the

Language Templates of your favorite synthesis software tool.

For more information on VHDL standard libraries refer to the Appendix.

3.3 Architecture

The VHDL entity declaration, introduced before, describes the interface

or the external representation of the circuit. The architecture describes

what the circuit actually does. In other words, the VHDL architecture

describes the internal implementation of the associated entity. As you can

probably imagine, describing the external interface to a circuit is generally

much easier than describing how the circuit is intended to operate. This

statement becomes even more important as the circuits you are describing

become more complex.

There can be any number of equivalent architectures describing a single

entity. As you will eventually discover, the VHDL coding style used inside

the architecture body has a significant effect on the way the circuit is

synthesized (how the circuit will be implemented inside an actual silicon

device). This gives the VHDL programmer the flexibility of designing sys tems with specific positive or
negative features such as particular physical
size (measuring the number of needed basic digital elements) or operational

speed.

For various reasons, such as facilitating code re-usability and connectibil ity, an architecture can be
modeled in different ways. Understanding the

various modeling techniques and understanding how to use them represent

the first important steps in learning VHDL.

An architecture can be written by means of three modeling techniques

plus any combination of these three. There is the data-flow model, the

behavioral model, the structural model and the hybrid models.

These models will be described throughout the book. Listing 3.5 gives a

sneak preview of what a simple but complete VHDL code block looks like.

3.4 Signal and Variable Assignments

In VHDL there are several object types. Among the most frequently used

we will mention the signal object type, the variable object type and the

constant object type. The signal type is the software representation of a

wire. The variable type, like in C or Java, is used to store local information.

The constant is like a variable object type, the value of which cannot

be changed. A signal object can be of different types; we saw before, for

example, that a signal object can be of type std logic or of other types

like integer, custom types, etc. The same applies for variable objects.

Before using any signal or variable, it is mandatory to declare them.

Signals are declared at the top of the architecture body, just before the

keyword begin. Variables must be declared inside the process construct

and are local. An example is shown in line 14 and 17 of Listing 3.5.

As seen in line 19 and line 20 of Listing 3.5 when you want to assign a new

value to an object of type signal you use the operator “<=”. Alternatively,

when you want to assign a new value to an object of type variable you will

use the operator “:=”, shown in line 21.

It is important to understand the difference between variables and signals,

specifically when their value changes. A variable changes its value soon

after the variable assignment is executed. Instead, a signal changes its

value “some time” after the signal assignment expression is evaluated.

This has important consequences for the updated values of variables and

signals. This means that you should never assume that a signal assignment

can happen instantly and it also means that you can take advantage of

variables every time you need to implement a counter or to store values

when inside a process.

In order to be able to introduce the use of a variable we had to employ

the process construct, a construct that you are not yet familiar with. We

will see more in details later on in the book that any time we need a

non-concurrent execution environment where code lines are executed one

after the other (like in C or Java), we will be using the process construct.

Inside a process, all instructions are executed consecutively from top to

bottom. However the process itself will be executed concurrently with the

rest of the code (e.g. the instruction at line 24).

Always remember that the assignment of Listing 3.5 at line 24 and

the execution of the process, are not executed consecutively but instead

concurrently (all at the same time). Any hope that the execution of line

24 will happen before or after the execution of the process will only result

in great disappointment.

As a final note, let us to remind that the type std logic only exists if

you declare the library ieee.std logic 1164.all as done in line 4 of

Listing 3.5.

3.5 Summary

ˆ The entity declaration describes the inputs and outputs of your circuit.

This set of signals is often referred to as the interface to your circuit

since these signals are what the circuitry, external to the entity, uses

to interact with your circuit.

ˆ Signals described in the entity declaration include a mode specifier and

a type. The mode specifier can be either an in or an out (or, as we will

see later on, even an inout) while the type is either a std logic or

std logic vector.

ˆ The word bundle is preferred over the word bus when dealing with

multiple signals that share a similar purpose. The word bus has other

connotations that are not consistent with the bundle definition.

ˆ Multiple signals that share a similar purpose should be declared as

a bundle using a std logic vector type. Bundled signals such as

these are always easier to work with in VHDL compared to scalar types

such as std logic.

ˆ The architecture describes what your circuit actually does and what

its behavior is. Several possible implementations (models) of the same

behavior are possible in VHDL. These are the data-flow model, the

behavioral model, the structural model as well as any combination

of them, generally called hybrid model.

3.6 Exercises

1. What is referred to by the word bundle?

2. What is a common method of representing bundles in black-box

diagrams?

3. Why is it considered a good approach to always draw a black-box

diagram when using VHDL to model digital circuits?

4. Write VHDL entity declarations that describe the following black-box

diagrams

VHDL Programming Paradigm

The previous chapter introduced the idea of the basic design units of VHDL:

the entity and the architecture. Most of the time was spent describing
the entity simply because there is so much less involved compared to the

architecture. Remember, the entity declaration is used to describe the

interface of a circuit to the outside world. The architecture is used to

describe how the circuit is intended to function.

Before we get into the details of architecture specification, we must step

back for a moment and remember what it is we are trying to do with VHDL.

We are, for one reason or another, describing a digital circuit. Realizing

this is very important. The tendency for young VHDL programmers with

computer programming backgrounds is to view VHDL as just another pro gramming language they want
or have to learn. Although many university

students have used this approach to pass the basic digital classes, this is

not a good idea.

When viewed correctly, VHDL represents a completely different approach

to programming while still having many similarities to other programming

languages. The main similarity is that they both use a syntactical and rule based language to describe
something abstract. But, the difference is that

they are describing two different things. Most programming languages are

used to implement functionalities in a sequential manner, one instruction at

a time. VHDL however describes hardware and so instructions are executed

in a concurrent manner1

, meaning that all instructions are executed at

once. Realizing this fact will help you to truly understand the VHDL

programming paradigm and language.

4.1 Concurrent Statements

At the heart of most programming languages are the statements that

form a majority of the associated source code. These statements represent

finite quantities of actions to be taken. A statement in an algorithmic

programming language such as C or Java represents an action to be taken

by the processor. Once the processor finishes one action, it moves onto the
next action specified somewhere in the associated source code. This makes

sense and is comfortable to us as humans because just like the processor,

we are generally only capable of doing one thing at a time. This description

lays the foundation for an algorithmic method where the processor does

a great job of following a set of rules which are essentially the direction

provided by the source code. When the rules are meaningful, the processor

can do amazing things.

VHDL programming is significantly different. Whereas a processor steps

one by one through a set of statements, VHDL has the ability to execute

a virtually unlimited number of statements at the same time and in a

concurrent manner (in other words, in parallel). Once again, the key

thing to remember here is that we are designing hardware. Parallelism, or

things happening concurrently, in the context of hardware is a much more

straightforward concept than it is in the world of software. If you have

had any introduction to basic digital hardware, you are most likely already

both familiar and comfortable with the concept of parallelism, albeit not

within a programming language.

Figure 4.1 shows a simple example of a circuit that operates in parallel.

As you know, the output of the gates are a function of the gate inputs.

Any time that any gate input changes, there is a possibility that, after an

opportune delay, the gate output will change. This is true of all the gates

in Figure 4.1 or in any digital circuit in general. Once changes to the gate

inputs occur, the circuit status is re-evaluated and the gate outputs may

change accordingly. Although the circuit in Figure 4.1 only shows a few

gates, this idea of concurrent operation of all the elements in the circuit is

the same in all digital circuits no matter how large or complex they are.

Since most of us are human, we are only capable of reading one line of

text at a time and in a sequential manner. We have the same limitation

when we try to write some text, not to mention enter some text into
a computer. So how then are we going to use text to describe a circuit

that is inherently parallel? We did not have this problem when discussing

something inherently sequential such as standard algorithmic programming.

When writing code using an algorithmic programming language, there

is generally only one processing element to focus on at each given time.

Everything more or less follows up in a sequential manner, which fits nicely

with our basic limitation as humans.

The VHDL programming paradigm is built around the concept of ex pression parallelism and
concurrency with textual descriptions of circuits.

The heart of VHDL programming is the concurrent statement. These are

statements that look a lot like the statements in algorithmic languages but

they are significantly different because the VHDL statements, by definition,

express concurrency of execution.

Listing 4.1 shows the code that implements the circuit shown in Figure 4.1.

This code shows four concurrent signal assignment statements. As seen

before, the “<=” construct refers to the signal assignment operator. It is

true that we cannot write these four statements at the same time but we can

interpret these statements as actions that occur concurrently. Remember

to keep in mind that the concept of concurrency is a key concept in VHDL.

If you feel that the algorithmic style of thought is creeping into your soul,

try to snap out of it quickly. The concurrent signal assignment is discussed

in greater detail in the next section.

As a consequence of the concurrent nature of VHDL statements, the

three chunks of code appearing below are 100% equivalent to the code

shown in Listing 4.1. Once again, since the statements are interpreted as

occurring concurrently: the order that these statements appear in your

VHDL source code makes no difference. Generally speaking, it would be a

better idea to describe the circuit as shown in Listing 4.1 since it somewhat

reflects the natural organization of statements.

4.2 Signal Assignment Operator “<=”

Algorithmic programming languages always have some type of assignment

operator. In C or Java, this is the well-known “=” sign. In these languages,

the assignment operator signifies a transfer of data from the right-hand side

of the operator to the left-hand side. VHDL uses two consecutive characters

to represent the assignment operator: “<=”. This combination was chosen

because it is different from the assignment operators in most other common

algorithmic programming languages. The operator is officially known as

a signal assignment operator to highlight its true purpose. The signal

assignment operator specifies a relationship between signals. In other

words, the signal on the left-hand side of the signal assignment operator is

dependent upon the signals on the right-hand side of the operator.

With these new insights into VHDL, you should be able to understand the

code of Listing 4.1 and its relationship to its schematic shown in Figure 4.1.

The statement “G <= A AND B;” indicates that the value of the signal

named G represents an AND logic operation between the signals A and B.

There are four types of concurrent statements that are examined in this

chapter. We have already briefly discussed the concurrent signal assignment

statement which we will soon examine further and put it into the context

of an actual circuit. The three other types of concurrent statements that

are of immediate interest to us are the process statement, the conditional

signal assignment and the selected signal assignment.

In essence, the four types of statements represent the tools that you will

use to implement digital circuits in VHDL. You will soon be discovering

the versatility of these statements. Unfortunately, this versatility effectively

adds a fair amount of steepness to the learning curve. As you know from

your experience in other programming languages, there are always multiple

ways to do the same things. Stated differently, several seemingly different

pieces of code can actually produce the same result. The same is true
for VHDL code: several considerably different pieces of VHDL code can

actually generate the exact same hardware. Keep this in mind when you

look at any of the examples given in this tutorial. Any VHDL code used to

solve a problem is more than likely one of many possible solutions to that

problem. Some of the VHDL models in this tutorial are presented to show

that something can be done a certain way, but that does not necessarily

mean they can only be done in that way.

4.3 Concurrent Signal Assignment Statements

The general form of a concurrent signal assignment statement is shown in

Listing 4.5. In this case, the target is a signal that receives the values of

the expression. An expression is defined by a constant, by a signal, or by

a set of operators that operate on other signals. Examples of expressions

used in VHDL code are shown in the examples that follow.

This example contains a few new ideas that are worth further clarifica tion.

ˆ There are header files and library files that must be included in your

VHDL code in order for your code to correctly compile. These few lines

of code are listed at the top of the code in Listing 4.6. The listed lines

are more than what is needed for this example but they will be required

in later examples. To save space, these lines will be omitted in some of

the coming examples.

ˆ This example highlights the use of several logic operators. The logic

operators available in VHDL are AND, OR, NAND, NOR, XOR and

XNOR. The NOT operator is technically not a logic operator but is

also available. Moreover, these logic operators are considered to be

binary operators in that they operate on the two values appearing on

the left and right-hand side of the operator. The NOT operator is a

unary operator and for that, it only operates on the value appearing to

the right of the operator.

ˆ In this solution, the entity only has one associated architecture. This is
fairly common practice in most VHDL design.

Example 1 demonstrates the use of the concurrent signal assignment (CSA)

statement in a working VHDL program (refer to line 12 of Listing 4.6).

But since there is only one CSA statement, the concept of concurrency is

not readily apparent. The idea behind any concurrent statement in VHDL

is that the output is changed any time one of the input signals changes.

In other words, the output F is re-evaluated any time a signal on the

input expression changes. This is a key concept in truly understanding the

VHDL, so you may want to read that sentence a few more times. The idea

of concurrency is more clearly demonstrated in Example 2.

This example shows a one-line implementation of the given logic equation.

An alternative solution to Example 2 is provided in Figure 4.8. This

example represents an important concept in VHDL. The solution shown in

Listing 4.8 uses some special statements in order to implement the circuit.

These special statements are used to provide what is often referred to as

intermediate results. This approach is equivalent to declaring extra variables

in an algorithmic programming language to be used for storing intermediate

results. The need for intermediate results is accompanied by the declaration

of extra signal values, which are often referred to intermediate signals.

Note in Listing 4.8 that the declaration of intermediate signals is similar

to the port declarations appearing in the entity declaration, except that

the mode specification (in, out or inout) is missing.

The intermediate signals must be declared within the body of the archi tecture because they have no
link to the outside world and thus do not

appear in the entity declaration. Note that the intermediate signals are

declared in the architecture body but appear before the begin statement.

Despite the fact that the architectures f3 2 and f3 1 of Listing 4.7 and

Listing 4.8 appear different, they are functionally equivalent. This is because

all the statements are concurrent signal assignment statements. Even

though the f3 1 architecture contains three CSAs, they are functionally

equivalent to the CSA in f3 2 because each of the three statements is

effectively executed concurrently.

Although the approach of using intermediate signals is not mandatory

for this example, their use brings up some good points. First, the use

of intermediate signals is the norm for most VHDL models. The use of

intermediate signals was optional in Listing 4.8 due to the fact that the

example was modeling a relatively simple circuit. As circuits become more

complex, there are many occasions in which intermediate signals must be

used. Secondly, intermediate signals are something of a tool that you will

often need to use in your VHDL models. The idea here is that you are

trying to describe a digital circuit using a textual description language: you

will often need to use intermediate signals in order to accomplish your goal

of modeling the circuit. The use of intermediate signals allows you to more

easily model digital circuits but does not make the generated hardware

more complicated. The tendency in using VHDL is to think that since

there is more text written on your page, the circuit you are describing

and/or the resulting hardware is larger or more complex. This is simply

not true. The main theme of VHDL is that you should use the VHDL

tools at your disposal in order to model your circuits in the simplest way

possible. Simple circuits have a higher probability of being understood and

synthesized. But most importantly, a simple VHDL model is not related

to the length of the actual VHDL code.

In Example 2, the conversion of the logic function to CSAs was relatively

straightforward. The ease with which these functions can be implemented

into VHDL code was almost trivial. Then again, the function in Example 2

was not overly complicated. As functions become more complicated (more

inputs and outputs), an equation entry approach becomes tedious. Luckily,

there are a few other types of concurrent construct that can ease its
implementation.

4.4 Conditional Signal Assignment when

Concurrent signal assignment statements, seen before, associate one target

with one expression. The term conditional signal assignment is used to

describe statements that have only one target but can have more than one

associated expression assigned to the target. Each of the expressions is

associated with a certain condition. The individual conditions are evaluated

sequentially in the conditional signal assignment statement until the first

condition evaluates as true. In this case, the associated expression is

evaluated and assigned to the target. Only one assignment is applied per

assignment statement.

The syntax of the conditional signal assignment is shown in Listing 4.9.

The target in this case is the name of a signal. The condition is based

upon the state of some other signals in the given circuit. Note that there is

only one signal assignment operator associated with the conditional signal

assignment statement.

The conditional signal assignment statement is probably easiest to un derstand in the context of a
circuit. For our first example, let us simply

redo Example 2 using conditional signal assignment instead of concurrent

signal assignment.

There are a couple of interesting points to note about this solution.

ˆ It is not much of an improvement over the VHDL code written using

concurrent signal assignment. In fact, it looks a bit less efficient in

terms of the number of instructions.

ˆ If you look carefully at this code you will notice that there is in fact

one target and a bunch of expressions and conditions. The associated

expressions are the single digits surrounded by single quotes; the as sociated conditions follow the
when keyword. In other words, there is

only one signal assignment operator used for each conditional signal
assignment statement.

ˆ The last expression in the signal assignment statement is the catch-all

condition. If none of the conditions listed above the final expression

evaluate as true, the last expression is assigned to the target.

ˆ The solution uses relational operators. There are actually six different

relational operators available in VHDL. Two of the more common

relational operators are the “=” and “/=” relational operators which

are the “is equal to” and the “is not equal to” operators, respectively.

Operators are discussed at greater length in further sections.

There are more intelligent uses of the conditional signal assignment state ment. One of the classic uses
is for the implementation of a multiplex

The next example is a typical conditional signal assignment imple mentation of a MUX

There are a couple of things to note in the solution provided in List ing 4.11.

ˆ The solution looks somewhat efficient compared to the amount of

logic that would have been required if CSA statements were used. The

VHDL code looks good and is pleasing to the eye, qualities required

for readability.

ˆ The “=” relational operator is used in conjunction with a bundle. In

this case, the values on the bundle SEL are accessed using double

quotes around the specified values. In other words, single quotes are

used to describe values of individual signals while double quotes are

used to describe values associated with multiple signals, or bundles.

ˆ For the sake of completeness, we have included every possible condition

for the SEL signal plus a catch-all else statement. We could have

changed the line containing ’0’ to D0 and removed the line associated

with the SEL condition of “00”. This would be functionally equivalent

to the solution shown but would not be nearly as impressive looking.

Generally speaking, you should clearly provide all the options in the code

and not rely on a catch-all statement for intended signal assignment.

Remember, a conditional signal assignment is a type of concurrent state ment. In this case, the
conditional signal assignment statement is executed

any time a change occurs in the conditional signals (the signals listed in

the expressions on the right-hand side of the signal assignment operator).

This is similar to the concurrent signal assignment statement where the

statement is executed any time there is a change in any of the signals listed

on the right-hand side of the signal assignment operator.

Though it is still early in the VHDL learning game, you have been

exposed to a lot of concepts and syntax. The conditional signal assignment

is maybe a bit less intuitive than the concurrent signal assignment. There

is however an alternative way to make sense of it. If you think about

it, the conditional signal assignment statement is similar in function to

the if-else constructs in algorithmic programming languages. We will

touch more upon this relationship once we start talking about sequential

statements.

The concept of working with bundles is very important in VHDL. Gener ally speaking, if you can use a
bundle as opposed to individual signals, you

should. You will often need to access individual signals within a bundle.

When this is the case, a special syntax is used (e.g. SEL(1)). Note that

the code shown in Listing 4.12 is equivalent to but probably not as clear

as the code shown in Listing 4.11. Be sure to note the similarities and

differences.

4.5 Selected Signal Assignment with select

Selected signal assignment statements are the third type of signal assign ment that we will examine.

As with conditional signal assignment state ments, selected signal assignment statements only have
one assignment

operator. Selected signal assignment statements differ from conditional

assignment statements in that assignments are based upon the evaluation

of one expression. The syntax for the selected signal assignment statement

is shown in Listing 4.13.

One thing to notice about the solution shown in Listing 4.14 is the use of

the when others clause as the final entry in the selected signal assignment

statement. In reality, the middle clause ’0’ when ’0’ could be removed

from the solution without changing the meaning of the statement. In

general, it is considered good VHDL programming practice to include all

the expected cases in the selected signal assignment statement followed by

the when others clause.

SOLUTION. This is a repeat of Example 4 except that a selected signal

assignment operator is used instead of a conditional signal assignment

operator. The solution of Example 6 is shown in Listing 4.15. The black-box

diagram for this example is the same as before and is not repeated here.

Once again, there are a few things of interest in the solution for Example 6

which are listed below.

ˆ The VHDL code has several similarities to the solution of Example 5.

The general appearance is the same. Both solutions are also much more

pleasing to the eye than the one where the MUX was modeled using

A when others clause is used again. In the case of Example 6, the

output is assigned the constant value of ’0’ when the other listed

conditions of the chooser expression are not met.

ˆ The circuit used in this example was a 4:1 MUX. In this case, each of

the conditions of the chooser expression is accounted for in the body

of the selected signal assignment statement. However, this is not a

requirement. The only requirement here is that the line containing the

when others keywords appears in the final line of the statement.

The only comment for the solution of Example 7 is that the vertical bar

is used as a selection character in the choices section of the selected signal

assignment statement. This increases the readability of the code as do the

similar constructs in algorithmic programming languages.

Once again, the selected signal assignment statement is one form of a

concurrent statement. This is verified by the fact that there is only one

signal assignment statement in the body of the selected signal assignment

statement. The selected signal assignment statement is evaluated each

time there is a change in the chooser expression listed in the first line of

the selected signal assignment statement. Re-evaluation also occurs every

time there is a change in a conditional signal on the right-hand side of the

signal assignment operator.

The final comment regarding the selected signal assignment is similar

to the final comment regarding conditional signal assignment. You should

recognize the general form of the selected signal assignment statement

as being similar to the switch statements in algorithmic programming

languages such as C and Java. Once again, this relationship is examined in

much more depth once we are ready to talk about sequential statements.

with the previous solutions to this example is that they required the

user to somehow reduce the function before it was implemented. In this

modern day of digital circuit design, you score the most points when you

allow the VHDL synthesizer to do the work for you. The solution to this

example hopefully absolves you from ever again having to use a Karnaugh

map, or God forbid, boolean algebra, to reduce a function. The equivalent

expression for F3(L, M, N) = L · M · N + L · M and its Karnaugh map is

shown below. The solution of Example 8 is shown in Listing 4.17.

4.6 Process Statement

The process statement is the final signal assignment type we will look at.

Before we do that, however, we need to take a few steps back and explore

a few other VHDL principles and definitions that we have excluded up

to now. Remember, there are a thousand ways to learn things. This is

especially true when learning programming languages, where there are

usually many different and varied solutions to the same problem. This is

highlighted by the many different and varied approaches that appear in

VHDL books and by the many tutorials.

So, now is not the time to learn about the process statement. We will do

that right after we pick up a few more VHDL concepts. Now just remember

that the process statement is a statement which contains a certain number

of instructions that, when the process statement is executed, are executed

sequentially. In other words, the process statement is a tool that you can

use any time you want to execute a certain number of instructions in a

sequential manner (one instruction after the other, from top to bottom).

Do not forget, however, that the process statement in itself is a concurrent

statement and therefore will be executed together with the other concurrent

statements in the body of the architecture where it sits.

4.7 Summary

ˆ The entity/architecture pair is the interface description and behavior

description of how a digital circuit operates.

ˆ The main design consideration in VHDL modeling supports the fact that

digital circuits operate in parallel. In other words, the various design

units in a digital design process and store information independently of

each other. This is the major difference between VHDL and higher-level

computer programming languages.

ˆ The major signal assignment types in VHDL are: concurrent signal

assignment, conditional signal assignment, selected signal assignment

and process statements. Each concurrent statement is interpreted as

acting in parallel (concurrently) to other concurrent statements.

ˆ The process statement is a concurrent statement that contains a series

of statements which will be executed in a sequential manner, one after

the other. A programmer uses a process statement when he wants to

execute some commands in a sequential manner.

ˆ The architecture body can contain any or all of the mentioned concurrent statements.

Signals that are declared as outputs in the entity declaration cannot

appear on the right-hand side of a signal assignment operator. This

characteristic is prevented from being a problem by the declaration

and use of intermediate signals. Intermediate signals are similar to

signals declared in entities except that they contain no mode specifier.

Intermediate signals are declared inside the architecture body just

before the begin statement.

ˆ Generally speaking, there are multiple approaches in modeling any given

digital circuit. In other words, various types of concurrent statements

can be used to describe the same circuit. The designer should strive for

clarity in digital modeling and allow the VHDL synthesizer to sort out

the details.