Elektor 1996 01
Elektor 1996 01
2.65
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THE INTERNATIONAL
ELECTRONICS MAGAZINE
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01
3} 7 407
X1 5.00:n 3.55n x12 -= :herriat. Generate a PCB rats -nest from a schematic
1.1
The Personal Edition gets you started with schematic & PCB
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are included. with support for 2 copper layers & 1 silk screen
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Designer £149
111 The Designer Edition of OR 3.5 includes schematic capture &
automatic generation of a PCB 'rats -nest'. Routes can then be
manually routed. and checked against the schematic. The full
manual is also included.
January 1996
ELEK 11 °
' -LEEN
7- CONTENTS Vohune 22
Numbe r 240
ISSN 0268/4519
Front cover By
.. Sami Karim]lahtt
:.. 0 di 4"
course we start this month
begins with a general COMPUTERS & MICROPROCESSORS "'"NI a..
,
it, ' 401 e'
. - t^
' - ti
k
20
Design by M. BrOggenwirth
PROJECT: Synchronous oscillators
Y'lc,t- 44i,
,a ,
=) Hi
Design by T. Giesberts
. -.4...".k T
1141_
"Ir...".. -"wee,
RADIO, TV AND COMMUNICATIONS
24 PROJECT: Secam-to-PAL converter
-
Design by T. Giesberts
Secam-to-PAL converter -p.24
TEST & MEASUREMENT
76 PROJECT: Passive -component tester (for use with
-
an oscilloscope) ,
From an idea by R. Veltkamp -...*- n Wiwi
. _
' 7 ..
7.7, i.e."...
44 From the World of Electronics 4
""._
o ell
ABC
AUDIT BUREAU Of CIRCULABORS
82
70-72
Index of advertisers
Readers' services II t ' - a
41 Switchboard
CONSUMER PRESS Passive -component tester - p. 7(i
Elektor Electronics is published monthly, except in August, by Elektor Electronics (Publishing), P.O. Box 1414. Dorchester, Dorset DT2 SYH. England. 7 he maeazine is
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[Link]: please send address corrections to Elektor Electronics. do Mercury Airfreieht International Inc. 2323 Randolph Avenue, Avenel. New Jersey. NJ. 07001.
--
ELEKTOR ELECTRONICS JANUARY 1996
6 Please mention ELEKTOR ELECTRONICS when contacting adverti3er.,
:. :1,-13
t 11 -1-2.. 1,21=3,10 Mir.
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and requires EASY -PC Professional
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For full information, please write, phone or fax: - TECHNICAL SUPPORT FREE FOR LIFE
PROGRAMS NOT COPY PROTECTED.
Number One Systems SPECIAL PRICES FOR EDUCATION.
UKiEEC: Ref. EK HARDING WAY, [Link], CAMBS., ENGLAND. PE17 4WR. e-mail: sales@[Link]
Telephone UK 01480 461778 (7 lines) Fax: 01480 494042 International +44 1480 461778
USA: Ref. EK, 126 Smith Creek Drive. Los Gatos, CA 95030
Telephone/Fax: (415) 968-9306
1!!!!!!!I
programming
console
supply
outputs AD/DA fast counter BCD
card multiplexers voltage
monitor
Fig. 1. Block diagram of a typical industrial PLC. The function of the blocks shown here is discussed in the text.
[Link] F. I. EC FRONICS JAN L ARV 1996
8 ERS/MICROCONTROLLERS
Bit and register memories may be ways. Most inputs. however, are com-
found in most PLCs. These memories patible with direct voltages between
enable current values of variables to 0 V and 24 V. In rare cases. PLC in-
be stored while the program is being max. 40V puts may even be suitable for direct
executed. A special location is reserved connection to the mains. Figure 2
for the accumulator. which is a regis- H
shows the input characteristic of a
ter used by nearly all instructions. typical PLC input using switching lev-
The register memory allows the typ. 24V els of 0 V and 24 V. Note that the range
storage of different types of number. between 8 V and 15 V is not defined.
both binary and BCD. The size of the min. 15V Apart from differences as regards the
memory location may be8 bits (byte) input voltage levels. PLC inputs may
or 16 bits (word). Register memories mat.. BV
also be classified according to the
are mainly used for the processing of presence or absence of electrical isola-
analogue signals. and the reading and OV tion. The drawing in Fig. 3 shows how
processing of BCD values. If available a 24-V PLC input may be provided
in the PLC. timers. counters and shift with electrical isolation. The permissi-
registers also make use of the internal ble input voltage may lie between
registers. -40 VDC and +10 VDC. The inputs are
The user memory contains the code symmetrical for direct voltages as well
for the application program to be run as RF noise. The integrated RF filter
by the PLC. Usually. this is a RAM area suppresses noise caused by electro-
with battery backup. In many cases. magnetic interference. The actual elec-
PLCs also allow the user program to be min. -40V trical isolation goes on account of an
stored in EPROM or EEPROM. A spe- opto-isolator. whose output signal is
cial ZIF socket then enables system ii -X4 t - 12
filtered by a simple RC network which
developers to supply a PLC which is introduces a delay of 8 to 10 ms.
tailored and ready -programmed for a Thanks to this delay, even pulsating
specific application. signals applied to the input are recog-
The text memory is used to define Fig. 2. The switching levels pertaining to a nized as a direct voltage.
a number of messages which the PLC. PLC input are clearly defined. Only a level
depending on certain situations. sends between +8 V and +15 V does not have a
to a terminal or a printer, with or with- clear logic level.
About outputs
out additional information. It is usu- The outputs of a PLC are used to
ally possible to incorporate the register switch loads such as magnetic valves.
contents or the time into the message. small motors and signal lights. Just as
Here is an example of such a message: Manual mode: this enables outputs to with the inputs. PLCs differ in respect
be switched on and off manually. This of the practical realization of their out-
*** ERROR 04 *** Oven temperature function comes in handy while testing puts. Usually. the outputs have either
too high! fans, valves, signal lights. etc. which an open collector, a relay or a triac.
are connected to the PLC's output. Most open -collector outputs are capa-
The watchdog increases the stability ble of switching voltages between 5
of the applications running on the About inputs and 36 VDC at a maximum current of
PLC. As soon as the watchdog is ac- 1 A. Here. too. there are versions with
tive, the PIC program is forced to ad- Ordinary PLC inputs play an impor- and without electrical isolation.
dress the timer at certain intervals. If tant role in the process of reading In practice, there is a large differ-
that does not happen in time, for in- switch states and detector states. ence between switching the positive
stance. when the system has crashed, Depending on the application. PLC in- voltage and switching ground via
the watchdog is actuated, and gener- puts may be realized in a number of open -collector outputs. With switching
ates an alarm signal for the user. If de-
sired, the watchdog may also generate
a signal to re -initialize the PLC. and re-
start the user program.
Voltage
-5 to +5 V
-10 to +10 V
0 to +5 V
0 to +10 V
Current
-20 to +20 mA
0 to +20 mA
+4 to +20 mA
Finishing touches
It is sometimes required for the user to
be able to change certain parameters.
for instance, delay times. wile the pro-
gram is running. For that purpose,
most PLCs have an externally accessi-
ble switch whose state is interrogated
frequently by the program. Thanks to
Fig. 4. The left-hand section of this drawing (a) shows the results of a short-circuit to ground this arrangement. it is not necessary
on a an open -collector output which switches to ground. The right-hand section (b) shows to re -program the PLC any time one of
you what happens if an output is used which switches the supply voltage. the parameters has to be changed.
The PLC is usually programmed via
a special programming console. This
ground, a short-circuit to ground (sys- titles such as pressure, electrical volt- separate unit contains a display and is
tem chassis) may cause unwanted ac- age and current. temperature. speed. only connected to the PLC during pro-
tuation of the load (Fig. 4a). This may rotational speed. etc. The opposite is gramming It allows parameters to be
give rise to very dangerous situations. also possible. i.e.. a card may be used modified, a program to be loaded, the
Switching the positive voltage (Fig. 4b) to drive analogue loads such as fre- memory to be examined, and any er-
has no such risks. if such an output is quency controls, power controls, and rors to be removed from the program.
active. and a short-circuit to ground positioning systems. The A -to -D card A standard feature on all modern
occurs, the protection in the supply converts an analogue electrical value PLCs is a communication interface in
line will be actuated. It is then impos- (voltage or current) supplied by. for ex- the form of a serial port. This may be
sible for the actual load to be actuated ample, a sensor, into a digital value (at an RS232, RS485. or current loop
erroneously. It will be clear that this a resolution of 8. 12 or sometimes even type. Using this port. the PLC commu-
type of safety precaution is essential in 16 bits). With the aid of a D -A card, the nicates with peripherals such as ter-
the industrial environment where ca- PLC is capable of generating analogue minals, printers. measurement
bles and equipment are subject to voltages. The voltage and current equipment, or a PC. An optional bar-
heavy mechanical stress. ranges used for analogue signal pro- code reader is an important aid when
Counting quickly
As a result of their relative slowness. Station Definition
PLC inputs can not be used to count Station name (opt SMAPCD
more than about 100 pulses per sec- 1. OK
ond. Hence. special cards have been de- Address (11..121il. 2 Cancel 1
A -D and D -A cards
These cards are employed whenever
the PLC has to process analogue quan- Fig. 5. An industrial PLC from Landis & Gyr.
the system is programmed to sort STL as STH, however the level read is DEC decrements counter by 1.
products on a conveyer belt in a ware- inverted before it is copied into the ac- CCR compares contents of counter to
house. cumulator. specified operand. If the two are equal.
ANH performs a logic function between the accumulator is set. If not. the ac-
Vanity features the current accumulator contents and cumulator is cleared (reset).
the level read from the specified input. JMP jumps unconditionally to the
Today's PLCs may be taken up in a output, or aux. memory. specified location. Location should be
network just like PCs. but only if a ANL as ANH. however the AND func- between 16 and 63.
special network card is installed. In tion is performed between the current JIO jumps to specified location if accu-
principle. it is even possible to incor- accumulator contents and the inverted mulator has a high level. Location
porate PLCs into an existing PC net- level read from the specified input. should be between 16 and 63. If the
work. Furthermore.' a number of output. or aux. memory. accumulator has a low level, the pro-
special buses are in use. These so- ORH Performs a logic OR operation be- gram simply continues with the next
called field buses. for instance. tween the current accumulator con- instruction.
Interbus-S or Profibus, see rapid ac- tents and the level read from the J12 jumps to specified location if accu-
ceptance and increasing popularity. specified input. output or aux. mem- mulator has a low level. Location
Most PLCs have a modular structure. ory. should be between 16 and 63. If the
They consist of a basic system which ORL as ORH. however the OR function accumulator has a high level, the pro-
can be given extra functionality by is performed between the current ac- gram simply continues with the next
adding insertion cards. The basic sys- cumulator contents and the inverted instruction.
tem comprises a power supply. a CPU, level read from the specified input. WM wait as long as' specified input is
some memory and a limited number of output. or aux. memory. high. This instruction may not refer to
inputs and outputs. In some cases. XOR performs a logic XOR function outputs or aux. memories.
there is even a fast counter input and between the current accumulator con- WIL wait as long as specified input is
an AD/DA card. Modern PLCs can be tents and the level read from the spec- low. This instruction may not refer to
fitted with 128 inputs and outputs ified input, output or aux_ memory. outputs or aux. memories.
without problems. CPA inverts the current contents of WTO writes specified operand (be-
the accumulator. tween 0 and 63 binary) to the outputs
The Micro PLC OUT writes the level contained in the (6 to 11).
accumulator to the specified output or SEA. set accumulator.
After a cursory look at the structure aux. memory. REA reset accumulator.
and applications of industrial PLCs it SEO writes a high level to the specified RPM return from run mode to program
is time to get back to our Micro PLC. In output or aux. memory. mode.
the previous instalment we already REO writes a low level to the specified VER transmits software version num-
printed a quick rundown of the in- output or aux. memory. ber via the serial interface.
struction set. This month we discuss CPO inverts the level of the specified
each instruction in detail. output or aux. memory. External instructions in program-
DLY generates delays between 0.1 s ming mode
NOP no operation and 25 s. Operand indicates delay in
STH reads the specified input, output 0.1 s. chr(0) to chr(250): data; increased by
or the specified auxiliary memory. and ICR Copies specified operand into one (for acknowledgement) and re-
copies the contents to the accumula- counter. turned.
tor. INC increments counter by 1. chr(251): returns the status of inputs
0 to 5 as a binary number (0-63). fol-
lowed by a 'hash' character (#1.
chr(252): returns the status of out-
puts 6 to 11 as a binary number (0-
63). followed by a 'hash' character (#).
chr(253): expects a number between 0
and 63. and writes it to the outputs.
On completion of this instruction, a #
Is returned.
chr(254): transmits the software ver-
sion number in the form
CR/LF<string> CR/LF
chr(255) ends programming mode.
and switches to run mode.
About [Link]
The program is launched as follows:
[Link] [options] <enter>
you are presented with a number of Numerical value (preset value) before the actual
options, which may be selected via a allows the contents of one specific lo- program is started. This initialization
menu. cation in the buffer to be modified. is performed automatically when the
This method may be used to make menu options Download & Autostart'
Load Buffer with File minor changes to the program. The and 'Restart Program are selected.
prompts you for a file name, and user should ensure however that no
copies this file into the buffer. The invalid program steps are created. OFF
length of the file must be 48 bytes (as Turns the above option off. All outputs
generated by microplc). Program Microple are off when the program is started.
Download & Autostart
Save buffer to File Buffer data are sent to the PLC via the Reset Value
writes data contained in the buffer to a serial link. When this option is se- Enables the preset value on the out-
file specified by the user. If the speci- lected. the program waits for the user puts to be modified. The value is indi-
fied file name already exists, the user to reset the PLC. If the transmission of cated in binary form.
is notified. the buffer contents does not start
within two seconds after the PLC has Serial Port
Edit Buffer Contents been reset. the serial link has be allows you to change to another serial
Mnemonics checked. In that case. you may inter- port than the one stated when the pro-
allows the user to enter the program rupt the program by pressing any key. gram was invoked. You may select one
with the aid of mnemonics. Microplc of COM1 through COM4.
always starts from location 16. The Restart Program
program can be made to return to the allows you to switch the PLC to run Exit Microplc
main menu by typing END. The pro- mode when the program to be exe- leaves the program. and returns the
gram as 'entered is then available in cuted is already in the PLC's memory. PC to DOS.
numerical form in the buffer. Non - and the PLC itself is in programming
used program locations in the buffer mode. That concludes the description of the
are automatically filled with the instructions offered by the program.
value 26 (RPM. return to Program Preset Outputs Some practical programming examples
Mode). Because it is practically impos- ON will be discussed in next month's in-
sible to enter invalid instructions, this If on. this option causes the PLC out- stalment. (960001-1)
is the best way to enter PLC programs. puts to be initialised with a certain
ELEKTOR ELECTRONICS JANUARY 1996
12 Please mention ELEKTOR ELECTRONICS when contacting advertisers
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ELERTQR ELECTRONICS JANUARY 1996
14
COPYBIT INVERTER
lifilif s in go Mai zi zirm se =Nem rail ZIT WARNING. Fhe information in this
MI MI IIIII IN 1 0 MI MI MI SO IINI In ow orP, - iii 0.1 twi r article is intended solely for the
WO lb filo'
01.-.-- U
in is asir1I
M
MOW Pinups recording. processing and copying
of private musical work. The Editor
ID MP EV
i INIIIM n IN
as RE WI i and Publishers disclaim all respon-
MEI 1W1 MI MI .7: sibility for any use that may in-
fringe any copyright vested in com-
-.' 1111111 mercial compact discs and (digital)
Nolialillik
---- 1 i' if, 1 tape cassettes.
111b,vol um so
Category code
The coding of the S/PDIF has been de-
scribed in detail in the article on the
'copybit eliminator'. The following de-
scription is therefore limited to the most
important aspects of it.
In all domestic audio equipment. the
format uses sample frequencies of32 kHz,
44.1 kHz and 48 kHz. These data con-
tain. among others. information as to the
copybit. The format reacts to the con-
tent of the S/PDIF. The SCMS. which in-
The copybit eliminator published in the February 1994 issue of hibits multiple (digital) copying of the
source signal. can be bypassed as shown
this magazine has two drawbacks. The first of these is that it in the flow diagram in Fig. 1. It is not
cannot be used without modifying the digital audio equipment. sufficient to invert only copybit 1. As
The second is clear from the revisit to the eliminator in the the diagram shows, when copying with
category code 00 000 000 (general) takes
September 1995 issue: from time to time, the eliminator needs place. for instance, the copybit is not
updating - it is not 'future -proof'. The copy -permit converter sampled. This means that the record-
described in this article does not have these drawbacks ing has to be passed through a copybit
eliminator a second time. It is. therefore.
much safer to set the copybit to (or hold
it at) 1 and assign to it the category
Design by W. Foede nal so modified is accepted by the code of an apparatus whose copybit is
recorder as if it comes from a cD always sampled.
player (so that unlimited copying of The present inverter always out-
T ike the copybit eliminator pub- the signal becomes possible). The in- puts the category code of a DAT or a
verter also offers a number of other CD. depending on the input signaL
1...dlished in this magazine in the Feb-
ruary 1994 and September 1995 is- facilities. such as S/PDIF detection. The code changes automatically. so
sues. the copybit inverter is an inex- that the subdata in the USER channel
pensive and simple -to -build circuit for
inverting the copybit in a digital
S/PDIF* audio signal to enable users Brief specification
to copy (digitally) their own musical Opening or modification of the audio equipment not required
work many times without degradation 'Future -proof. since it is independent of the category code
by the SCMS**. Unlimited (digital) copying of source material
Optical or coaxial inputs and outputs as required
The inverter can be included in the S/PDIF detector
S/PDIF link between any digital a.f. Indication of the position of the copybit and automatic setting to (= digital
1
* Sony/Philips Digital Interface Format - the consumer version of the AES/EBU standard. This standard was devised by
the American Audio Engineering Society and the European Broadcasting Union to define the signal format. electrical
characteristics and connectors to be used for digital interfaces between professional audio products.
** Serial Copy Management System.
ELEKTOR ELECTRONICS JANUARY 1996
COPYRIT INVERTER 15
FRAME 0
propmble, 0
..........
20 (18) bit audio data L
right -h
VU CPI Preamn{e W
0101010101010101 16 BIT AUDIO DATA R
IVIulcIP
RESERVE LSE LS3 CONTROL
BIT o r. cN o ri
FRAME 1
FRAME 191
, 4:1
0101011 01010 0 0 o to 0
I
SUBFR
FRAME e I COPY I^ I ^I CD ORIGINAL -I I RI n)
PERMIT
GENERATION BIT
(ORIGINAL) step2 00
2x audio w/o 00X0 Mode 0 00 GENERAL 0000000 X
13 with pre -emphasis 00X1 Mode 1 10 CD 1000000 0
1000 ppm
14 studio use 1XXX MD 1001001 0 44.1 kHZ 0000 step3 01
15 not 2x audio X1XX DAT 1100000 1 48 kHz 0100 12,5
16 copy disabled XXOX DCC 1100001 1 32 kHz 1100 stool 10
17 copy allowed XXIX DSR 0011000 0 50 ppm
PCI.1 0100000 1
AID 0110000 X
only 1 bit is mentioned per frame (SF L SF R) 910104 - 12
nal independent of the polarity at the the dwell times of the monostables are bits is in synchrony with the bit clock
input, since all subsequent steps are in accord. The block clock is stretched and is reset by the subframe clock.
related to the XOR signal. The spacing to a constant -1 signal (NOINv) by ICid Filtering the desired bits (bit 30 in
of the positive edge in ease of a logic 0 and ICie: its presence is indicated by bubirzumet, 4. 5. and 1.0--31) io a_fc.,...ted
is 354 ns and in case of a logic 1. D10. If, for instance, the signal has an by programmable 1C2. The INVERT
177 ns-see Fig. 5. incorrect frequency. NOINV prevents it pulse has the correct position when
Normally. the clock is retrieved by a being modified and this is indicated signal itsti is delayed by about 60 ns
phase -locked loop. PLL. which, as far by Dio lighting less brightly. The LED (IN2). A logic 1 is indicated when the
as time and phase ratios are con- does not light at all when the input relevant LED is driven by the level de-
cerned. is not easily kept stable. signal is not of the S/PD1F formal tector signal output by 1C2. This sig-
Moreover, the voltage -controlled oscil-. To count the subframes. a 9 -bit nal is generated in a manner similar
lator. vc0, remains operational in the counter is timed by the subframe to that of the block clock. Each
absence of an input signal. which clock and reset by the block clock. D-bistable associated with a given LED
makes decoding of the block and sub - The 5 -bit counter for the subframe is reset by the block clock and set
frame clocks more complicated.
The XOR signal starts non-retrigger-
able monostable IC3a, which has a r ---
dwell time of about 240 ns. to retrieve LED indications
the bit clock. In the range of the pre-
ambles, the start spacings are Only D9 lights in both switch positions: ready for use: no S/PDIF
>350 ns. This is made use of by retrig-
gerable monostable IC3b, which has a LEDs flicker: unit is not operating correctly. It may be that both inputs are used
mono time of around 420 ns. to gener- simultaneously. or that the input signal is not of the correct format. or that the setup
ate the subframe clock. The x -coded is incorrect. or that the optical input receives spurious signals.
XOR pulse occurs only with the block . D9 and D10 do not light: unit functions as converter: S/PDIF signal is transferred
preamble at the first pulse of the sub - unchanged.
frame clock. This enables the block
clock to be decoded. 0. D10 lights brightly: the S/PD1F input signal. with copybit and category, is indi-
The block clock is generated regu- cated The output signal is DAT when the input comes from a magnetic tape drive. and
larly when the circuit operates as CD when comes from any other source. In both cases. copying is permitted.
specified, that is, when there is a digi-
tal input signal in S/PDIF format, and
ELEKTOR ELECTRONICS JANUARY 1996
COPYBIT CONVERTER 17
with the 1 -signal. The period to the
BIPHASE MARK ENCODING next reset is long enough to enable
the LED indicating the in a stable
1
source data
way (without flickering).
O 1. 1 I a 71 tIRZ 'eye! Inversion of the bit is accomplished
153 was
by an XOR gate and the 354 ns long
biphase mark n
10,011,01,110 1 0.110,0 '1,1
n n nn , 0,1 bit cells
the bit can, however, not be avoided
entirely. This does not matter, how-
ever. since the biphase-modulated sig-
I I t I 0 I I 1 1 I source data nal is always sampled at the centre of
950104 - la a bit -cell, that is. at 1/3 and 2/3 of
the bit.
When bit C8 and C9 in the input
4 SPDIF PREAMBLES signal are logic I (magnetic tape
e1eek preamble 0 0.1
drive), they will not be affected. All
sz
other signal sources are assigned the
code of a CD player.
I I I SalitaiNal preamble M (1) Moreover, bits 0 and 1 of the
IS
channel status are held at logic 0. Al-
though this is not really necessary in
I I I l I
tra-170 precertele W (3) domestic equipment (since the bits
NIce04 I
suttrame !XI /
,
0 I 1.
,I 2 1 3
I
1
r00
1.3101 - 14
then are always logic 0). it makes it
possible for professional recordings or
other recordings marked by these bits
(which are inhibited) to be copied-but
see warning at beginning of this
5 article.
U C P block preamble B
With switch Si open, the inverter
IN1
0 0 0 0 0 accepts sampling frequencies of
354ns 532ns
44A kHz and 48 kHz. but with 32 kHz
it must be closed to alter the time
constants of the monostables. If this
IN2
switch is in the wrong position, Dg
and dimly lit D10 indicate that the sig-
120ns nal is unchanged: the unit functions
EXOR as a converter. A no -signal condition
is indicated by D9 lighting.
Istart MF (non-ret iggerable) It is highly improbable that only the
generation bit, which does not count
MF1 0 240ns in the equipment coding, is encoded.
bit clock 2.822 MHz (354 ns)
Anyway, there is always D10 as a con-
start MF2 (retriggerable) trolling element.
The output is buffered by inverter
MF2 0
n 420ns 1-1
IC* Resistors R4 and R5 lower the sig-
subtrarne clock (88.2 kHz (11.34 its) nal level to about 0.5 VPP into 75 LI
Capacitor C1 blocks any direct volt-
BLOCK age.
II
block clock 229.7 Hz (4.35 ms)
550101- 17 Timing the monostables
Construction of the inverter on the
6 SUOFRAME 4 SUBFRA1E 5 birs,c).
Nock plermuce W
Y U C P
0
O
0112 Fig. 3. Biphase coding enables the si-
BIT:17) ICe 3101331S1 multaneous transmission of the
has) WC
INVERT n INVERT
audio signal and the clock.
EXOR Fig. 4. Various waveforms of a non-
0112
- COPY
biphase coded preamble.
C
CPTO CUT
OPTO
C
5 -SIT TRAVER
SAMPLE FREO. BIT CS1T
11:12
00.01
r
CTR
COAX CUT
10. C SIT INVERT T CCIIT ItiV
IC3 1C2 9b. LCOIC INVERT BUFFER
PL13_
MAO
TCLc
SLCCC DISPLAY LED
LMIC 1-10
ICI rrCa
IC2 EPI17222 IEPLO1 SLOG(
1C3 1-04539 DETECT
seIoi C 419
ICI
printed -circuit board in Fig. 9 should wire bridge underneath IC2. from a CD player set to PAUSE (which
not present any undue difficulties. All After the board has been finished ensures a very stable signal) to the co-
ICs. except IC6. should be seated in and thoroughly checked. set the pre- axial input socket. Set switch S1 to
sockets. Be careful with inserting IC2 sets to the centre of their travel. 44.1/48 kHz, whereupon D3 (category
into Its PLCC socket. Do not forget the Apply an audio signal. preferably code CD) should light. If an oscillo-
TA
5V
IC6
5V
IC1 =74HC04
IC5
4704 IC3 =74HC4538
TORX173
04
ZOOn
BI = B80C1500
811
T15 23 35
39011
13 39 SF4 4+
RIS
11 37 SF16
5 33 SF18 03.41- 3
05
12
14
1C2
28 SF24 1/-
28 SF26 0IA4-1161
-II. 06 6
7
0
aali MIM
16 24 SF28 .4-."11 -*Da a
700p TOO p 17
19
EP1A7032
LC44-15
20 SF30 139
18 SFDIF Nif 9
81 1k
21 27
5V 010
R14
25 32 L
IC d a 111 !Cie
NOON 4 34
R12
SI
R13
1 BLOCK 36
Is
COPY
4.4 38
10
012 013 40 41 ,r1C11
2 3
1110n
2 s 1114148 43
P2 P3 DI I CIS
4k7 4k7
C12 C11 RIO 10 22 30 42
014148 100n
2
2 100p 14 22p 15 014 IMO
1/14148
RCX CX SV
Jl 12 10 La
IC3a
3 14F1
47TH
3 cx CIO
EXOR 0021
SVet MF2
"C7 C1,',
purposes, these settings are fine. Rt 10
If more accurate settings of the pre- 01 10 1C3
C
Parts list
Resistors:
RI, R2 = 10 MI
R3, R4, R8 = 100 f2
R5 = 270 f2
R6. R7 = 680 fl Fig. 10. Finished prototype board.
ELEKTOR ELECTRONICS JANUARY 1996
20
SYNCHRONOUS OSCILLATORS
en a digital -to -analogue con- 1 2
verter (DAC) is used in conjunc- RI
tion with a CD player, their clocks R3
5V C7
tor IC2 continues to work when ICia is 14
IC3
14 II 1
IC3c IC3d
to the crystal. If the value of this re- 7
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-3dB. Damping Factor >300, Slew Rate 45inuS,
T.H.D. typical 0.002%. Input Sensitivity 500mV. S.N.R.
-110 dB. Size 300 z 123 z SOmm.
PRICE C40.85 C3.50 P&P
SECAM-TO-PAL CONVERTER
The circuit described in this article is, in principle, an add-on by the blocks marked 'SECAM decoder'
for the popular Picture -in -Picture (PIP) Processor featured in and 'PAL decoder'. The remainder of
the circuitry shown is. well. necessary
the October and November 1995 issues of this magazine. to make it all work! The SECAM de-
Because the PIP prodessor has only a PAL decoder. it is codes is a type TDA8395. This is a fully
unable to display a colour inset picture in countries where the integrated decoder, complete with RF
and LF filters. a PLL demodulator and
SECAM TV system is used. That problem may be overcome by a line identifier. The IC functions with
inserting the present converter between the inset source and a minimum number of external com-
the PIP processor. The circuit offers more goodies. however, ponents and requires no adjustment.
As a baseband delay line, the manu-
particularly for owners of satellite TV receiver systems. facturer recommends the TDA4661
(IC9) - yes. the one used in the PIP
processor also. The same goes for the
practical realization of the block
marked 'sync. circuit', because it is
based on the TDA2579B (IC5).
The most important function in the
circuit, the encoding of the PAL signal
is performed by a TDA8501. This is an
almost entirely integrated encoder IC
specially designed for all applications
requiring the conversion of R. G and B
(or Y. U and V) into PAL or NTSC val-
ues. The external parts required to
make the TDA8501 work are limited to
two delay lines and a reference oscilla-
tor.
For the following description of the
operation of the circuit we recommend
keeping one eye on the block diagram
because the signal paths in it are prob-
\t/ ably easier to trace than those in the
actual circuit diagram. The latter is
ALSO FOR shown in Fig. 2. and is drawn such
RGBTOPAL that the position of the elementary
parts is about the same as those in the
block diagram.
SECAM dissected
The SECAM/CVBS signal which ar-
Design by T. Giesberts rives on socket Kt is applied to pin 16
of SECAM decoder ICI via jumper JP4.
The outputs of the decoder (pins 9 and
10) supply the modulated colour dif-
NIE 71-1ILE this circuit was being devel- unit supplies the input signals for the ference signals. Since only one colour
V V oped. it became clear that it converter. Obviously, the synchroniza- difference signal is transmitted per
could have more functions than just tion of the inset picture requires the line in the SECAM system (the two
converting SECAM to PAL. The PAL en- CVBS signal of the TV to be fed back to colour difference signals are actually
coder used here is capable of modulat- the PIP unit. This option has been transmitted alternately). a delay line is
ing colour difference signals as well as taken into account in the practical re- necessary to join the two signals again
RGB signals. and in addition offers a ali7ation of the converter. for each TV picture line. That is. ad-
`fast switching mode between these mittedly. not ideal. but it is inherent to
two options. Obviously, this present:, A few blocks only the SECAM system (see the inset box).
the possibility to convert. RGB signals The result is that one of the colour dif-
into PAL format. But that's not all! The Although integrated circuits have been ference signals is never actually up to
present converter also doubles as an used wherever possible in the practical date. Obviously. that creates errors in
interface between the PIP unit and circuit. the actual circuit diagram is determining mixed colours. By con-
older TV sets. By 'older we mean tel- quite complex. So. we give you a block trast, the current colour differences do
lies which do have a SCARF connector diagram first to make sure you can un- get transmitted in the PAL system, re-
at the back, but lack the required 'fast derstand how the circuit works. The sulting in much better picture quality.
blanking and `ROB' inputs on this block diagram in Fig. 1 gives a good For proper operation of the SECAM
connector. In that case, the present indication of the structure of the con- decoder it was found necessary to put
converter is inserted between the PIP verter. the levels of the horizontal and vertical
unit and the TV set, so that the PIP The heart of the converter is formed blanking at about half -way the sand-
ELEKTOR ELECTRONICS JANUARY 1996
SECAM-TO-PAL CONVERTER 25
corruption whatsoever of the signals.
SECAM K1 Incidentally. IC4 has to supply 6 dB of
additional gain to compensate the at-
tenuation of the delay line. Because
CVBS SECAM
.C2
baseband
CS
sync
the exact gain may vary a little, it is
B -Y)
decoder delay line circuit adjustable (within a small range) with
preset P2. The 4.4 -MHz trap at the
[Link] t input of IC4. R90-CIT-Li. already sup-
fast
presses a large part of the colour infor-
blanking
R
mation contained in the SECAM
C
G
signal. before this is applied to the PAL
RGB C decoder as a Y signal. The function of
1_ a
C delay line DL1 is to compensate the
status
propagation delays of the colour differ-
ence signals incurred in IC1 and IC2. A
L type DL330 delay line is used because
delay I a delay of 330 ps was found to be the
optimum value. However. when we
PIP K2 started to use standard RGB signals, it
R -03-Y) 4 was found that the CVBS signal sup-
CY) -03 if 4 plied by [C6 was only 60% of its nomi-
Ice
CVBS a
PAL nal value. If problems occur because of
f cvas
encoder
delay
this signal reduction, the solution is to
increase the value of R3. Ri and R5 to
c\as 120 0.
status
mug ar
0
M3 00000 -nrr
ade
1[22 24
ram
is
-*
SV
O
ay.
0
a fn
va=if
r+
TE123ILI
er i,7
C>
re
V as
24.1
r sV
C>
ICI =
2.41.1121.12..
is C> as
alb rat.
oa cla Mw
C 011_./ 4.. VIE
23.4.4 rta
Fig. 2. This is the complete circuit diagram. including the power supply and all connections. Connector K9 has been added to enable the con-
verter to be extended with an extra PAL decoder.
Pin 16 of 106 supplies the encoded switch/buffer/amplifier. The IC has Different modes
PAL/CVBS signal. In addition to this, two outputs: one 'ordinary' (pin 2). and
the TDA8501 also provides separate Y one switched video output (pin 6). The After the conversion from SECAM to
and C outputs. These are bonded out former supplies a buffered copy of the PAL (mode 1). the translation from
via buffers T3 and T4 and a mini -DIN PAL/CVBS signal applied to pin 3: this RGB into PAL (mode 2) is probably the
socket. This S -VHS socket should. output signal is fed out via Ks. for most frequently used feature of the
however, be considered as a kind of which a cinch or BNC socket may be converter. In support of this second
'bonus' for test purposes etc., because used. The signal at the other output of mode. jumper JP1 allows the fast
the quality of the output signal is IC7 (pin 6) depends on the switching blanking signal from K1 to be inter-
rather poor for lack of proper filtering level applied to pin 5. When a low level rupted. and to set the PAL encoder
and clipping. Moreover. the signal con- is applied, pin 6 is connected through permanently to RGB via the 'multiplex
tains a measurable residue of the to the PAL/CVBS signal at pin 3. A high switch control input' (pin 2).
SECAM 'colour information. By con- level causes the video (or CVBS) signal Obviously, the RGB source connected
trast, the CVBS signal is pretty clean. arriving via K1 to be switched through to K1 should then supply the sync
mainly because of a notch filter, L2 - (amplified) from pin 8 to pin 6. This is pulses (via pin 20). Both mode .1 and
C43, which affords excellent suppres- done to enable the incoming video sig- mode 2 require jumpers JP4, JP6 and
sion of the SECAM carriers. nal from a VCR in 'play' mode to be fed JP6 to be set to position 'A'.
IC7 is described by the manufacturer directly to K2. In case a SECAM signal As already mentioned. mode 3 en-
as a 'video switch'. Here. it actually arrives. that can be displayed in colour ables the PIP unit to be used in combi-
functions as a combined video on the TV set, via the PIP processor. nation with 'older' TV sets without
ELEKTOR ELECTRONICS JANUARY 1996
SECAM-TO-PAL CONVERTER 27
RGB and fast blanking input lines on 12-V supply voltage. straightforward, and mostly a matter
the SCART socket. This is accom- Finally. it should be mentioned that of locating the component on the com-
plished by setting jumpers JP4. JP5 a fourth mode is feasible. Those of you ponent overlay, soldering and cutting
and JP6 to position 'B'. Evidently. the who use a PAL TV set to watch SECAM wires. All essential connectors (in most
TV set should receive back its own satellite TV stations not only have the cases, only K1 and K2 will be used) may
sound. and that is why the audio input possibility to convert a SECAM signal be fitted straight on to the board. Only
signals are connected directly to the into PAL and use it as the parent K6. K7 and Kg are connected externally
output audio contacts of K2. By the ('main') picture (JP4 in position 'Al. but with short wires to the respective sol-
way, the extra (cinch) audio sockets. in addition may feed the TV's own PAL der pins. For the audio outputs be-
K4 and K5. are always connected to the signal back to the TV, through the PIP longing with the S -VHS option, K4 and
audio output signals of K2... unit (as an RGB signal), and employ it K5. both solder pins and cinch sockets
A few more remarks about mode 3. as an inset picture. Both the parent are available on the board. The pins
In this application (for PAL). the PIP and the inset picture then appear in and the sockets are not intercon-
processor supplies the input signals colour! As regards sound, a choice is nected, so may have to establish the
for the converter. As already men- available between
'parent picture' links yourself with the aid of two short
tioned, the synchronization of the sound and 'inset picture' sound. This lengths of screened cable.
inset picture requires the CVBS signal selection is made with the aid of JP5 Among the passive parts are eight
to be fed back from the TV set to the and JP6. The only condition for being inductors. Six of these, L3 through L8,
PIP processor. Hence, the circuit dia- able to use all these features is that the are ready-made miniature chokes. L1
gram shows pin 20 of K2 as connected TV set must be able to fully process the and L2 however are home-made, ad-
to pin 19 of K1. But that is not all. PAL signals that arrive via its SCART justable. inductors, built from type
Strictly speaking, this signal should be socket (in many cases, that can only be -7FIS assemblies from Neosid. Making
modulated again so that the inset pic- achieved via the antenna input). these inductors is not difficult because
ture and the TV picture can be joined there are no taps or secondary wind-
via the fast blanking feature of the PAL
Construction and power ings. L1 should have a value of about
encoder. If the main picture is to be supply 60 pH, and L2, 86 µH. These values
shown in colour, then an external PAL are achieved by winding 70.5 and
decoder is required, which may be The double -sided printed circuit board 84.5 turns of 0.1 -mm dia. enamelled
hooked up to the converter via connec- for the project is shown in Fig. 3. This copper wire on the formers, respec-
tor K9. All signals needed for that pur- board is available through the Readers tively. Be sure to solder the wire ends
pose are available on K9. including the Services (see page 70). Construction is to the right base pins, if necessary look
0 00
cc"741>°:,:or °O71
/Zi:
0dr,7tP0 -01
'1
Fig. 3. The printed circuit board has the same size as that of the PIP processor. and offers more than enough room for all components. If de-
sired. the power supply section. IC9. IC10. etc., may be cut off (board available ready made through he Readers Services. see page 70).
ELEKTOR ELECTRONICS JANUA RY 1996
28 RADIO/TELEVISION/COMMUNICATIONS
0
F0%000%0
0
°
000
000000040
,40,000000000:7)0C-)
°
0 a
a 00 0001 8' 8 8
a
0
-0000:;0 co 00
0 0
00
r0.,,AS) 000000
0
a (:)(93aNg9P0(8 0°88
a 0
COMPONENTS LIST
Resistors: C3 = 100pF D3 = 1N4148
R1-R5,R63,R71 = 7512 C4,C19,C45,C46 = 47pF 25V radial D4,D5 = 1N4002
R6,R30,R61,R62 = 41(127 C5 = 22nF ceramic D6 = low current LED
R7,R38,R50 = 5k116 C6,C7 = 1nF ceramic B1 = 880C1500 (straight)
R8,R11,R70 = 81d.-22 C8,C10,C24 = 22pF 40V radial T1 = BC547C
R9,R22 = 1501! C9,C11 = 10nF ceramic T2 = BC327
R10,R33,R35,R57 = 10kU C12,C13,C14,C16,C20,C32,C44,C47, T3,T4,T5 = BC337
R12,R13 = 1011 C48,C50,C52,C54,C56,C66,C67,C70, IC1 = TDA8395 (Philips)
R14,R15,R36,R49 = 100k52 C71 = 100nF ceramic IC2 = TDA4661 (Philips)
R16,R18 = 2ktIO0 1% C15,C49,C51 = 1pF 63V radial IC3 = AD827 (Analog Devices)
R17,R19 = 22111 1% C17,C59 = 22pF IC4 = AD847 (Analog Devices)
R20 = 11;118 C18,C31,C53 = 220pF 25V radial IC5 = TDA2579B (Philips)
R21 = 47k0 C21 = 330nF, 5mm IC6 = TDA8501 (Philips)
R23 = 5600 C22 = 150pF IC7 = TEA2014A (SGS-Thomson(
R24,R25 = 116100 1% C23 = 2pF2 63V radial IC8 = 74HCU04
R26 = 14752 1% C25 = 6pF8 35V tantalum IC9 = 7805
R27 = 14052 1% C26 = 47nF, 5mm IC10 = 7812
R28,R32,R34,R37 = 1k11. C27,C28,C30 = 100nF, 5mm
R29 = 12kt1 C29,C78 = 2nF2, 5mm Miscellaneous:
R31 = 82052 C33-C39,C74-C77 = 47nF ceramic JP1,JP2 = 2 -pin PCB header with
R39 = 2252 C40...C42 = 220nF, 5mm juniper.
R40,R51,R54,R58 = 1k0.2 C43 = 15pF JP3-JP6 = 3 -pin PCB header with
R41 = 27k5l C55,C57 = 220pF 10V radial jumper.
R42,R46 = 39ki1 C58 = 10pF trimmer K1,K2 = SCART socket, PCB mount.
843,874 = 150kt1 C60 = 27pF K3 = 4 -way mini -DIN socket, PCB
R44,R45 = 1ki110 1% C61,C63 = 4pF7 mount (SVHS).
R47,R67 = 221<c2 C62 = 10pF K4,K5 = cinch socket, PCB mount,
R48 = 220U C64 = 47pF e.g. T -709G (Monacor'Monarch).
R52,R55,R59 = 1kt15 C65,C69 = 10pF 63V radial K6 = cinch socket, chassis mount.
R53,R56,R60 = 6812 C72 = 1000pF 25V K7,K8 = see text.
R64,R66,R68 = 2M522 C68,C73 = 1000pF 16V K9 = 10 -way boxheader
R65 = 2K22 K10 = 2 -way PCB terminal block,
R69 = Inductors: raster 5mm.
R72 = 100 5W L1 = 600H: 70.5 turns 0.1mm e.c.w. X1 = crystal, 4.433619MHz, C;,
R73 = 82k52 on 7F1S (Neosid) 20pF.
R75 = 31(529 L2 = 86pH: 84.5 turns 0.1mm e.c.w. DL1 = DL330 (Philips)
P1 = 10k51 preset on 7F1S (Neosid) DL2 = DL470 (Philips)
P2 = 500 preset L3,L4,L6,L8 = 47pH choke Printed circuit hoard, order code
P3 = 100kt1 preset L5,L7 = 22pH choke 950078-2 (see page 70).
Capacitors: Semiconductors:
C1 = 100nF, raster 7.5 mm D1 = 5V1 zener, OW5
C2 = 220nF, raster 7.5 mm D2 = 8V2 zener, OW5
at the component overlay. secondary voltage (applied to K10) is If you do not envisage using the op-
Although it did not seem to be much lower at about 9 V. This voltage tional S -VHS connection. that section
strictly necessary on the prototype. is used to keep the dissipation in the of the board may be cut off without
screening may be fitted around the os- 5-V section of the supply within safe problems.
cillator section on the board. This sec- limits. However, because the 9-V a.c.
tion (IC8 and surrounding parts) is from the transformer is too low for the Adjustment
bordered by five holes intended for sol- 12 V regulator. it is first doubled by a
der pins which sen'e to hold pieces of cascade circuit consisting of D4 -C73 - Once the board has been built up and
tin-plate in place. If you want. you may D5 -C72. To ensure the best possible checked. the mains transformer may
also fit a cover on the screening. If you cooling. the heatsinks on regulators be connected to Km. and the converter
do. remember to drill a small hole so IC9 and IC10 should be mounted a little may be taken into use. No special tools
you can access trimmer C55 with a above the circuit board. That is easily or equipment are required at this
trimming tool. achieved with a small spacer. an extra point. although a plastic trimming tool
The power supply is also accommo- nut. or similar. With IC9. such a con- may be useful to set Li and L.,.
dated on the PCB. Referring back to struction is even essential to ensure Start by setting the jumpers to the
the circuit diagram. you will notice that the fixing hole of the PCB remains positions which correspond to the
that the power supply looks different accessible. standard mode of the converter. So:
from that in the PIP unit. Although the The layout of the board allows the JP' and JP2 closed. JP3 in position T
converter's power supply is also based power supply section to be separated and JP3 in position 'A'. Do not inter-
on two fixed voltage regulators. one for from the main circuit. where K3. K4 connect the PCB pins marked 'RGB'!
5 V and one for 12 V. the transformer's and K5 may remain in their positions. Turn preset P1 about 36 clockwise, and
ELEKTOR ELECTRONICS JANUARY 1996
30 RADIO/TELEV1SION/CONIMUNICAT1ONS
FM B-V
demodulator -IP
V
_=CAM
delay
A
-a-
e12
P2. P3 and trimmer C58 to about the maximum suppression of both carri- consider. however. that the converter.
centre of their travel. Turn the cores in ers. based on its function. may be fitted
L1 and L2 so that their tops just pro- Fitting the converter board into a into the same enclosure as the PIP
trude from the formers. In most cases. case is left to your own ingenuity. Do processor! (950078-3)
this adjustment will be fine. and no
further action is necessary.
Next, connect a SECAM signal to K1.
and a PAL TV to K2. Use fully wired
SCART cables for both connections.
Switch on the converter, and turn
P1 until the picture synchronization is
optimum. By turning the preset. try to
find the extremes which still give a
synchronized picture. and then set the
preset exactly between these extremes.
Next, adjust trimmer Css for the best
possible picture quality. preferably
using a plastic trimming tool. Then try
to find the settings on P2 and P3 which
give the best possible picture quality.
In most cases. these adjustments will
be uncritical. For the ideal setting of
gain adjustment P2. you may also mea-
sure the output video signal at pin 19
of K2. The measured level should be
1 Vpp into 75 11.
Finally. there are Li and L2 which
may require fine adjusting. These in-
ductors serve to suppress residual lev-
els of the SECAM signal. and should
be adjusted for minimum interference
in the output picture. Owners of an os- Fig. 4. In spite of its high degree of integration. the converter does contain a respectable
cilloscope may adjust the cores for number of components.
£325
Erasers PB-10 Programmer
& pin Low cost programmer.
EPROMs, E2PROMs, Flash and 8748/8751.
convertors Fast programming algorithms.
AT - Chiprase Simple but powerful menu driven software.
Ultra -violet eraser.
Very compact £139
16 chip capacity
Built in tinier £95 SMART Communications have a full
range of dedicated programmers for
Pin convertors the Microchip PIC range of
from DIL to microcontrollers - both single and
PLCC, SOP, SOIC etc... gang for DIL and SO1C variants.
from f50
We also supply a wide range of development tools - Assemblers, Compilers, Simulators
and Emulators - for a wide range of microprocessors, especially the Microchip range.
Our ROM emulators start at just £99.
aPAARTCOMMUNICATIONS
2 Field End Arkley Barnet Herts EN5 3EZ England
Telephone +44 (0)181 441 3890
Fax +44 (0)181 4411843
VISA
36
u,
use
T
- Usu
U3
.1111-
950101-11
Fig. 1. Block diagram of a simple function generator Fig. 2. Timing diagram of the integrator signal. U1. and of the
with additional analogue input via R. rectangular output signal. Ua, of the comparator.
ELEKToR ELECTRONICS JANL-ARy 1996
TRIANGULAR WAVEFORM GLNERATOR AS ADC 37
charge current of C1. Thus. provided
P1 is set correctly. the charging and
discharge times of Ci are equal. The IC1 = TLC2272 acs 5V
DS
tor. the value of C1. and the charging RI IC2
and discharge resistors,. provided 0-0-- 100k CUT
these are all constant, have no effect THR 555
on the duty factor, which is deter-
mined solely by the input voltage.
[00 TR
CV
5
Q Lit 11-4=316-5:57;)
= = 9
U MU
where LIU is determined by the two
peak values of the comparator. the ca- Fig. 3. The circuit of the analogue -to -digital converter comprises
pacitor is rharged (TA) and discharged two op amps and a timer.
(TE) in the time interval dt.
(I + /in)TA
puter must be at least a factor 29
Ub /3 TE -TA higher than the converter frequency.
Iin TE TA
(-/ + lin) TE Jimw. This allows the value of C1 to be
determined:
/3 The current /may be replaced by
29
Equalizing these two quotations and I- Ub
(if UR2 = Ub /
>
fcpu R2
solving for lin gives 3R2
The value of R1 must be chosen
(-I + lin) TE (I + lin) TA and lin by: such that the input signal can vary
-Ub /3 Ub / 3 within the desired limits.
ni
Software with three routines
Substituting these equations gives The necessary software consists of one
n=0
compute and two count routines-see
TE -TA Fig. 4-taking no more than a few
m=0 Ub
b
Um- blocks in a language like BASIC. The
counting loops should be sampled
Unlike the duty factor, the period (and about 4000 times (depending on the
thus the frequency) of the output sig- values of R2 and C1) in any measure-
nal depends on the peak values of the ment period. If the software is too
output voltage, the supply voltage and slow, or too fast, the value of C1 must
the value of C1. be altered accordingly. This changes
the measurement period (normally
Ub I about 200 ms). but it avoids rounding
T TA + TE = C
3 /2-11 off errors In the computation.
The program must. of course, not
1- (11n )2] be interrupted during the counting
f = 2CUb
31
loops. Unless an additional card with
I real-time timers is used, the PC is nor-
mally not able to drive the program.
1
1-1 Uhl 3R2 )2 After the converter has been con-
Ub R1 I nected to the PC, P1 must be adjusted
to give exactly 0 V at the open -circuit
To avoid large frequency fluctuations. output. Apply a known voltage. Ifni, to
the right-hand term should not exceed the input and turn P1 until 0 V is ob-
about 0.25. tained. The preset is not required if
the software provides scaling of the
Uin 3R2 indicated values. In this case. R3 must
Ub be 39 1c. Q.
19501011
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ATMEL AT89C2051
- 20 PIN - 8051 derivative
FLASH programmable (10004 limes)
- Erase program & verity
device in under 5 seconds
1> 0. 4.
(3) Accepts up to
(1) FAST data devic
transfer - ition
connects to PC
parallel port
11111r r er
i,-uppor!
(4) i4 (do
. ;
\ r.h I
A rzi fur pre_g
-.a co
micro ict
THE FULL ATMEL FLASH MICROCONTROLLER RANGE
8951 j 8952 1051 2051
FLASH code ROM I 4K 8K 1K 2K
RAM 128 256 64 128
I/O I
32 32 15 15
Timer/Counter (16 bit)
EQUINOX
2 3 1 2
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Short Course
8051/8032 Microcantrollers
304 Circuits and Assemblers
The fifth in the 300 Series of This course in book form de-
practical circuit book offers scribes the hardware and
a further selection of over software to make a complete SHORT COURSE
300 construction projects, de- microcontroller system. The
sign ideas, and practical ap- controller used is selected
plications from all aspects of from Intel's MCS-51 family.
electronics. In addition to an extensive
ISBN 0 905705 34 3 description of the controller
Price £ 12.95 board its ancillaries, the
book teaches the reader to
program MCS-51 microcon-
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with many examples.
Like its predecessors in the ISBN 0 905705 38 6
300 Series, 303 Circuits of- Price f 9.95
fers a comprehensive collec-
tion of practical ideas, con-
cepts and developments in the gamut of electronics. Unlike
its predecessors, the book is arranged in 11 subject sec- SMT Projects
tions to snake it easier for the reader to find that long - by Owen Bishop
sought circuit.
ISBN 0 905705 26 2 Price £ 10.95 This book describes the s e- SMT Projects
cial features of Sur ace
Mount Technology an how
302 Circuits to work with Surface Mount
Devices on the workbench. ,41111111
In well over 300 pages, 302 It includes over 20 con-
Circuits contains a variety of struction projects, all of
circuits for audio and video, which have useful applica-
car; home and garden; re- tions in and around the home
ceivers; hobbies and games; and workshop.
measuring and testing; oscil- ISBN 0 905705 35 1
lators and generators; power Price f 9.95 DeOcr Eiraftear,ci
supplies; microcomputers;
and a miscellany of other in-
teresting subjects.
ISBN 0 905705 25 4 Microprocessor
Price .1 9.95 Data Book
Originally compiled to meet
a need ofPlektor Electronics
301 Circuits engineers, technicians and
editorial stafffor a ready ref-
The second in the 300 Series of projects for construction at erence work on the most im-
home, in a small workshop or at school or college contains portant microprocessors, this
301 assorted circuits ranging from simple to fairly complex book contains data on not
designs, described and explained in straightforward lan- only modern devices, but also
guage. on older, well -established
ISBN 0 905705 12 2 Price f 9.95 types, such as the Z80 and the
6800.
ISBN 0 905705 28 9
Data Book 4: Peripheral Chips Price f 10.95
ISBN 0 905705 32 7 Price £ 10.95
Data Book 3: Peripheral Chips Data Sheet Book
ISBN 0 905705 30 0 Price 10.95 ISBN 0 905705 27 0 Price £9.95
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44
tions has been tailored to meet the de- under live seconds with no need for a uv
el ACIUMIlea 1.
eraser (guaranteed 1000+ reprogram-
I
Max11.
mand of the ever-changing market. To ming cycles). The device features 128
[Link]
assist customers, each product is ac- bytes of RAM, 15 1/o lines capable of di- arm MIME MB
companied by a brief description and rect LED drive, two 16 -bit
colour photograph. counter/timers and five interrupt
CPC is dedicated to service the in- sources. The standard 8051 serial tiART Pro' programming system, together with
dustrial and commercial user, but its has also been included. together with an a FREE Atmel AT89C1051 and a FREE
catalogue and service are becoming analogue comparator useful for A/D con- AT89C2051 microcontroller. data
Increasingly popular with other mar- versions. sheets. PSC, parallel cable and an ic ex-
ket sectors, such as education. The 'Micro Pro' has recently gained tractor tool for only £99. excl. vAT and
Another aspect of the CPC oper- official programming approval from the p&p. The offer ends on 31 December
ation is that customers need not Atmel Corporation for programming 1995. For further details call John Mar-
their complete range of FLASH microcon- riott on +44 1204 491 110. See also ad-
waste time looking for the part num- vertisement on p. 39.
ber they require. By simply ringing trailers. To celebrate the ascociation.
CPC's Partfinder Service, operators Equinox are offering an Atmel 'Micro
will access the vast and constantly ex-
panding database of 750.000 products
to find the parts you need. The highly
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Intelligent I/O and PLC from Cambridge Micro Systems MODBUS etc. The latter can also
be used for remote programming
A new low-cost industrial con- munications and networking. the and re -programming as well as in-
troller from CMS provides full sig- default is 10 ms. terfacing to most SCADA pack-
nal conditioning on each of CMS claim that at £95 in quantity ages and Visual BASIC. A
12 opto-isolated non -polarized in- this is the highest specified. lowest low-cost radio option is also avail-
puts and 4 isolated voltage -free cost controller available today. the able for remote locations or remote
outputs. The card can be pro- specification includes: 16/32 -bit networking.
grammed in Ladder Logic, or CPU 68000 compatible up to Cambridge Microprocessor
both, the latter offering full deter- 1 NI Byte of EPROM. and Systems Ltd., Unit 17-18 Zone D,
ministic control of the I/O but pro- 512 Kbytes of SRAM plus EEP- Chelmsford Road Ind. Estate.
viding the flexibility of 'C'. When ROM. 2 fast hardware timer/coun- Great Dunmow, Essex CM6
used as a PLC the user can select ters. on board PSU. expansion LXG. Tel. (01371) 875644, fax
the scan time required. for fast ap- options, 12C or NIBus. RS232 or (01371) 876077.
plications this can be as low as RS485 with full networking and
500 ps and still provide full corn - remote I/0 protocols such as (965013-1)
ELEKTOR ELECTRONICS JANUARY 1996
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3rd Prize
EIGHT -BIT LOGIC ANALYSER (UK)
a 28 -pin 300 -mil plastic DIP lected with four bits named
For PC Parallel Port case. Important features for A. B, C and D. With these
this project are: a 512x8 bit four bits the desired sam-
memory array structure. 15- pling rate is selected as
ns read/write cycle time (66 - shown in Table 1. A pro-
An 8 -hit 50 -MHz on PC parallel port Logic Analyser for MHz clock), and dual ports grammable counter con-
home application is always a useful tool for small for input and output data. I tained in the PAL can divide
digital projects, especially in field pP applications. decided to use this chip one of three input frequen-
(with 25 ns cycle time) for cies by 1, 10. 100 or 1000.
Eight bits with two triggers, 512 bytes and a maximum my application. The trigger section is also
sample rate of 50 MHz are good specifications for To tackle another prob- based on a PAL, and uses
hobby users. Low power and portability are also
lem, the triggering and time two direct signals from input
base. I selected a PAL from ch0 and chl. With four bits
important if you want to use this tool with a laptop Altera. type EP910. The time EO. TO. El and Ti we can
computer on the road. Optionally, you may use one 6 - base is built from a 2-5-10 select the trigger edge polar-
dual decade counter ity. Table 2 gives an
bit flash A/D converter at the input and so obtain a 74HC390 which produces overview of these settings.
combination of one analogue and two digital inputs. three output frequencies, Register 1 (CD4094) is
20 MHz. 8 MHz and 4 MHz. used to set all eight bits and
In the block diagram. select the mode of operation
Fig I, the signal from the for the Logic Analyser. To
By Jankijewic Ninoslav, el. ing. XTAL oscillator (40 MHz) read data from FIFO mem-
goes to the decade counter ory. a MUX (74HC157) is
and a selector which used with a control input (1,
My first idea was to make a sible. I had one sample of a switches the programmable low/high) to select and read
logic analyser with a very CMOS FIFO from IDT clock or the maximum clock four low or four high bits of
small number of compo- (Integrated Device Techno- from the XTAL generator. data.
nents, and as simple as pos- logy. Inc.) type IDT72210 in Programmable clock is se - The procedure to start
ELEKTOR ELECTRONICS JANUARY 1996
4_,Unifitt,COMPETITIONAMINNERS
Table 1
.4014
OSC 40MHz
A BCD RATE
Cu 20N
1.3
X SN 0 0 0 0 40 MHz
z
CI 414 0 0 0
D 1 20 MHz
0- LI
1 1 1 A 0 1 0 0 8 MHz
B 1 1 0 0 4 MHz
Clock Logic STROBE 1 0 1 0 2 MHZ
0. OUT DATA
CLOCK 0 1 1 0 800 KHz
CO O 1 1 1 0 400 KHz
IO
0.
F Ll 1 0 0 1 200 KHz
Tl
0 1 0 1 80 KHz
PAL
READ ENABLE 1 1 0 1 40 KHz
Clock Te FIFO FULL 1 0 1 1 20 KHz
RESET 0 1 1 1 B KHz
READ CLOCK 1 1 1 1 4 KHz
CHO cl Vcl RD FF Res Rd
-....<1...e__LOWHIGH DATA
a.
rt- -IP- INPUT DATA CHO/CH4
L
Clocked FIFO 512x8 x -le- INPUT DATA CHI/CH5
0. -IP-
-11.-
INPUT DATA CH2/CH6
ti INPUT DATA CH3/CH7
960301-11
CH7
Table 2.
0 x 0 A disable trigger
scanning the digital input. 250 mA at 40 -MHz sampling with a three -state buffer 1 0 x x +trigger ch0
read data and display it on rate. A 40 -MHz X1'0 and a (74HC125) which is also 1 1 x x -trigger 00
the PC screen is : buffer 74ACT04 are used for used for the trigger gate. x x 1 0 +trigger chi
the clock source. Digital Input signals are x x 1 1 -trigger ch1
1. Reset FIFO signal. RES=O. Frequency selection out- buffered by a standard
and reset FIFO read func- side of the PAL is achieved 74HC541 and then passed
tion. [Link]=1. At the same
time the trigger flipflop will
be reset.
2. Set trigger and time base
bits (Tables 1 and 2).
3. Reset FIFO signal. RES= 1. ("cc
4. Wait till FIFO Full Flag, TROK
FF=1. .11
5. Enable read FIFO func- COIF
_ILNORF
.Rec-81
tion, RD=1. . CH
211(7 .-1-43Pos-
HOT
(QO/Q7) in three steps: 0
MITP
O TRG834
a) output one read clock READ HOT
I 1)), 0 2
RCL: 'R0439
UDEe28
1 son.
b) read low data (4 bits from A OA
2
ON
NOT
J
C010
M UX): 8 OS .89
ANDS _0 .FF
c) read high data (4 bits C
E
OC
OD
SE
3S
Do LP 4 NORF
from MUX). F OF
5
7 ELKS
z
7. Display data on PC dis- I.- 14
G OG
OH
I 0
-13
play and go to step 1. 74139 -J OI
0.1
*Yce 1
. MX
n
OK
OL
on
ON
00 11-)13
ANO2 :
5
Y
CrJTP
xLce3
Hardware cLsete
CL 10419
is T .
OR2
.RA8
OUTP
The power supply may be an rip 0E833
external unregulated 9-V DC zits.
source. The board contains Ae37
1382 1
9E030142
trigger occurs, 22 /2
the FIFO C)
1,1
3
PAL
37 4 K1
25 DSUB
/5 2 5
input receives a one -clock 5 6
9._)
st
6
13
18
IIEP910 c
B
4 6
delayed signal which occurs 4
/10 D
17 0) 2
3
one clock before the trigger
action.
12
15
33 OE
0 E0 38
TO 36
714
13
O 3
3X1K
XL E1 35 12
The printed board is a sin- Ch 1 Ch2 TRG WOE RD T1
11
gle -sided home-made proa- 4 18
.5>H>Ti>13
1
16 4
C. 05 19 5
-,_r-mod 10
FIE0 04 18 11
separate signals like Read 110 CH41
14
6
7
In 15
14
3
D2
IDT72210
03 17
16
- -1=1-M19
11
12
114 CH2> 3 13
Clock and Fifo Full Flag from 32 8
N.
3 13
DS 02
15 14 441k
the computer a darlington 116 CH1>
It 8 CHO
3
11 9 12 9 5
04
DO
01
00 14 2
transistor array type 9
000000000E2
000000000 r
1
L 0 0 3
*gar
L.
J _
N r1 .-
-
00000000000 R(000000000) L-, 0
.0 4.-
+ 000000000 0) El c, 0
0
101
,...
0\\._o
_ 0000000000 9
-0 N\\%\ 0000000000
I
ix
\,:,
00 0 0 0lO1
? 1
00000000 O
. .% o o o o o o o o o o) d
o 0 o o o o o o o 0 r- 0
0-0-
0 0
o co
0
0
o
0
Pi
0 o o o o 3
LI01 ,-1 0 0 0 0
-* 00000000008 0 0 0 o S.
,c(rceo0. ..
0
0 0
o o
0
0
0
0
0
^0
0 a \-' o o a o 0
/I- j 0
0
0
0
0
0
0
0
0
0
0
0
0 4. 0
0
0
0
0 ,-'- 0
0 ry 0
00
0
-
S
0
0
0
0
VA'
0
0
0
0,0
o
0
o
0
6
0
0
0
0
01-0
000
0 0
0
0
0
Y.
0 0
ri 0 8 0 0 0
,
0 0
0-- -0 0A_ 0 00 0
0 0_,_0
o
--0 0
S:
O o co)
0 0
o CV
el(cr: 0 0 0-{ cc Fo Z
0-; : ito 00000000
0
(0000000E2)00
o o o o o 00 00000000 00000000
CG
931
0 901 L01
j
11:( .:2 r1)oo 0 0 0 0 o 0 0 9-.,,13 0 0 0 o 0 o 0 00000000
cr_00 0_
171>< cH c4 1-0
,.../0
UY a° ce°3 c)-( r I-0 U
000000000000
Samim,[Link] Is o oct
Table 3.
Components list
LPT1 pin signal port address function name
CX1,CX2,CX3,CX4 0.10
All R 141
1 STROBE out 37A bit 0 read clock for FIFO RCL
RN1 47ki1 network
2 DATAO out 378 bit 0 strobe for Register 1 STR
RN2 3413 network
3 DATA1 out 378 bit 1 Data for Register 1 DOW - C1 10pF tantalum
4 DATA2 out 378 bit 2 clock for Register 1 CL C2 33pF tantalum
5-8 DATA3-6 out 378 bit 3-6 not used 1N4002
9 DATA? . out 378 bit 7 select L/H data LOW/HIGH IC1
IC2
74HC541
74HC125
10 ACK in 379 bit 6 data input bit 317 03/07
IC3 74ACT04
11 BUSY in 379 bit 7 data input bit 2/6 Q2106
IC4 IDT72210.25
12 PE in 379 bit 5 data input bit 1/5 01/05
(clocked FIFO)
13 SEL in 379 bit 4 data input bit 0/4 00/04 IC5 74HC157
14 AFD out 37A bit 1 reset FIFO RES IC6 ULN2003
15 ERR in 379 bit 3 read FIFO Full Flag FF IC7 CD4094
16 INI out 37A bit 2 read enable for FIFO RD -OE IC8 EP910-25T (EPLD
17 SLC out 37A bit 3 not used PAL 40 -pin)
18-25
IC9 74E090
GND ground GND
1C10,1C11 74HC574
XTAL 40MHz. IC12 (M.
oscillator)
uA7805 IC13
D25 -SUB -90° K1
used here. The PAL's internal formed in Power Basic. The Analyser. The assembly code 20P-90° K2
diagram is given in Fig 2. test program was based on driver is linked with the
the information contained in BASIC program. and is used Programming files for this project
Software Table 3. for fast reading of the FIFO available on disk, see Readers
The final software is di- buffer, and displaying data Services page (p. 70).
Before started to write a vided in two parts. The main on the screen.
I (96030 1 )
driver in assembler. all program. written in BASIC.
hardware test were per- sets all modes for the Logic
BATTERY CHARGER
Small wind powered generators are useful devices for is 3 V. IC1b detects when The converter looks like a
the current rises to 10.4 A. resistor. Rin. of 0.57 ii to the
people dependent on battery power, such as and 'Cie detects when it generator. The outputs of
caravaners and yachtsmen. Commercial products are falls to 0.9 A. Both current IC1b and [Cie reset and set
expensive. The smallest models cost over £250. A levels are defined by the respectively the bistable
voltages from Rle. R3 and formed by the two NAND
generator giving up to 30 watts output can be made R4. and are proportional to gates 1C2b and lC2c. The set
using a permanent magnet radiator fan motor,
obtainable from a car breaker, costing about £5, a DC -
DC converter, described here, costing less than £15,
and an 800 -mm diameter wooden propeller described 30
0
by Mr. Piggott in Ref. 1. lit
20
Design by C. John Dakin
15 lsooRpAl
The DC -DC converter is nec- switch. T2. Each time T2 10 250
essau-y because the voltage the current
switches off,
output of the motor when which has built up in LI
used as a generator is much during the 180 vs T1 was
less than 12 V. the common- on. is steered into the bat- 0
est battery voltage. tery. BI. by D2. The current DO 02 0A as as ID 1.2
As shown by the circuit in LI is sensed by R11, a 10- Load Resistance. Ohms.
diagram in Fig. 2. the con- mcI resistor, and two voltage
verter uses an inductor. Ll. comparators. IC1b and IC lc
and a power MOSFET When the input voltage. V. Fig. la. Typical 12V car radiator fan motor power output power.
ELEKTOR ELECTRONICS JANUARY 1996
4a to 0 V. Ti's output drives the Ferroxcube core. A 0.6 -mm
six inverters of 1C3. 1C3 dri- air gap is put in the mag-
ves the gate of T2. which has netic circuit of the core
an input capacitance of using pieces of cardboard or
2 tiF. from 0 V to +12 V in other non-magnetic mater-
24 2 ps. ial. Each end of the winding
When Vi is rising from 0 V is connected to two pins of
2,s
to 2 V. ICIa's output stays the former. Sec the PCB lay-
C ts
low as pin 6 is above pin 7. out for the correct pins.
ICIb's and ICIc's outputs ZD 1. a BZY93C 16. 16-V.
to stay high as there is no cur- 20 -NV zener. should be fitted
rent through RI I. The if B1 may be disconnected at
bistable is forced to the reset any time. ZD1 will then limit
0
state by R5 and R6 holding the peak voltage at the drain
00 too '210 Asa pin 9 of IC2b low. When V1 of T2 to 17 V. ZD I requires a
WindspeecL MPH.
reaches 2 V. the output of suitable heatsink.
IC la goes high. the bistable Figure la shows the
is set and the first operating power output of a typical car
Fig. lb. Power output of the combined generator and converter cycle starts. Whenever Vi is fan motor when used as a
against wind speed. less than 2 V. Ti. IC3, C5 generator. The output is
and D2 draw only leakage maximum with a load of
current from the +12 V rail. about 0.4 fl. This equals the
pulse is via a third NAND parator. as long as VI is more The inductor in the circuit output resistance of the gen-
gate IC2a. the second input than 2 V. Setting the consists of 16 turns of 2 -mm erator. Rg. Because the con-
to which is held high by bistable switches T1 on and dia. enamelled copper wire verter losses increase as Rin
IC la. a third voltage corn- the collector falls from +12 V wound on an ETD39 decreases. Rin is set higher
R
10k
+Ui
R0kIc
+U1 +Ui T2 Gate
T2 Drain
+12U
4-13V
7V1 190uS n
1 OU
IC1b Pin 8 and
63000, ICIc Pin 10 01J+ TeilJ
3300
R3
+01 +Ui
IC3a-c ,f,
R8b,c,jd, 8UZ11
220CD I-0
CS
3SUleF
T INT Cl
1 3.5,7, 2.4, 1.-s
- 81 120
ZDI
R5 9.11, 10,12.
11N 14 15 Battery -
(e7r2U 4 R9 being
C2e T1
13CSIT
3713 charged
R4
300
-Ut
I /P R6
Q,
2
4 47k
3
C2
C2d TOOnF
"IV
960307-14
w53
Trailing edge
a +a q
le 2 Cut essay 1
kept as low as possible.
-0.-41- of trailing edge.
(950307-1)
0.7 1.1 1.6 2.2 3-I S 7 11 22 22 11 7 5 3-1 2.2 1.6 1.1 0 -Is -
I.8 2.7
Cut aria
1.9 5.4 8 4-----Thickness-----!,8
Cut away
in
oi References:
3.66 4 6.7 6-7 5.8 4.9 4 3.6 2.7 1.8Z
1. Scrapyard Windmill
Thickness
OP
Materiel Guenter say., Oregon Pine cr Pitch Pine
Finish 4-5 coots o, Polyurethane [Link]
Realities Building
iffinfifill 111101 Tools Collipers.5a,.nallot,Chosel,C,o,tniFe,Spoeeana,...5a,dosper Windmills with Recycled
Fit the propeller so that the c,r-ves side on le -e tisdca .a.c r4m4rnd
[Link] sewn C Shope bottoe feces
to an eel-cc...el section All disensions are .n noilieetres Parts by Hugh Piggott.
Published by The Centre for
Alternative Technology.
Machvnlleth. Powys. Wales
Fig. 3. Design of an 800 -mm propeller suitable for a typical fan motor. The reader is recommended to SY20 9AZ. Telephone:
read Mr. Piggott's excellent paper, Ref. 1. for full details of propeller design and construction. (01654) 702400.
COMPONENTS LIST
Resistors:
R1a-g 10k1/ SIL array
R2 3416
R3 3300
R4 3052
Copper Pattern viewed From Solder Bide. R5 18kfl
960307 -ELI R6 47kf/
R7 lokn
R8a-g 22052 SIL array
R9 3101.13
Bolt heatsink to PCB R10 680f2
RB
2eS "x1-5 - S G
R11 0.01Q (Farnell 148-
Heatsonk i.1T2 (:) 724)
R12 6f18
-L- It:3 --I RI01- (all single resistors metal film)
-r
Ce
1
-L1-
Capacitors:
C1 10mF 16V
02 bolted to heatsink
and PCB belou LI C2.C3,C4 100nF
t31 C5 lmF 50V
02
Inductor:
0.9"xlS" Heatslnk Ll 3C8 core, former
clip. ec wire 14SWG (2mm). Maplin
order codes: JR81C, JR82D, JR83E.
4.1
+Ui BL16S.
-I e2 11,11
Semiconductors:
Rli T1 BC547
RSIL1
22k
R2 CF,i235g292
10k VCC
3 488-71 L RE,(2R5UEEEl
U1
VPP PAO 20 Ral1 VCC
2 -I- C3 PA1 1k
47pF 47pF INT 2
PA2
EXTAL PA3
XTAL PA4
25
TIN PAS 28
PAB 7
FIST PA7
-014-2
PBO R8
FBI R7
PCO FB2 R8
PC1 P33 14 R5
10 PC2 FB4
1
R4 U2
IN4146 PC3 FES R3
PB6 R2 Lm7805
P87 RI VI VO
uF/63v 138705P3 C
10k
C4
CE
R5
0.1/63V
RICK
VCC AC
VCC 6a12v >
Opto2 R1EK/IN Opto RIEK/1W
871
BUZZER
G1
2N2222
Fig. 1. The circuit of the central heating system monitor is considerably simplified by a microcontroller. Here. a Motorola 68705P3 is used.
Translations: security = safety: bruleur = burner: acceterateur = accelerator.
ELEKTOR ELECTRONICS JANUARY 1996
60 DESIGN COMPETITION WINNERS
COMPONENTS LIST
P Resistors:
R1 = 8 -way SIL array 22 kit
R2 = 8 -way SIL array 10 K2
R3.R4,R5 =154t 1W
R6 = 12k11
Rail = 1kit preset
Capacitors:
C1 = 1pF 63V
C2,C3 = 47pF
C4 = 1000pF
C5 = 100nF 63V
C6 -C8 = 100nF 400V
Semiconductors:
D1 = 1N4148
D2 = bridge rectifier
D3.134,05 = 1N4001
D1 = 2N2222
Opto1.0pto2.0p1o3 = 4N25
U1 = 68705P3 (programmed)'
U2 = LM7805
Miscellaneous:
Y1 = quartz crystal 1MHz
B21 = buzzer
trot software.
The alarm output occu-
95030E -ELI pies one line of the other half
of port B. split into
inputs/outputs, and drives
a transistor which supplies
ra
SS the required current for the
buzzer. The other ports are
programmed to output
mode, and deliver the LC
0 MI display signals: eight -bit
data (Data, port A);
-C - data/command selection
(port C); and data strobe
^ T3
(port C).
The contrast of the LCD
module is adjusted by a pre-
set (the multiturn cermet is
not obligatory). The system
clock is derived from a
quartz crystal, Yl. Although
the clock will also function if
the crystal is replaced by a
resistor or a wire link, the
timing accuracy will drop
unless you modify the MOR
1
in software. The reset pulse
is supplied automatically by
capacitor C 1 when the sys-
tem is switched on. Diode
D l enables any voltage
higher than the supply volt-
043 age to be shunted away into
the power supply.
Printed circuit
950308-ES1 board
The circuit board is single -
Fig. 2. Component mounting plan and track layout for the PCB designed for the central heating monitor. sided. It has only seven wire
ELEKTOR ELECTRONICS JANUARY 1996
,DESIGN_COMPETITION WINNERS._
links, and accommodates all
parts except the power Sl1B01009CA6FFB704A6F0B705A6OFB7063F003F023F013F02A630B795
transformer. That gives you Sl1B011800AD6EA6OCB700AD68A606B700AD623F101102A680CDO1A1C9
a wide choice of power sup- S11B0130A601B700AD531002A620B700AD4BA620B700AD45A645B700BD
plies which may be used S11B0148AD3FA66EB700AD39A620B700AD33A656B700AD2DA665B70052
with the circuit. Most holes Sl1B0160AD27A669B700AD21A66C8700AD1BA66CB700AD15A665B7003D
arc drilled at a diameter of Sl1B0178ADOFA621B700ADO9A621B700ADO3CCO1A5A610CDO1A11202A2
0.8 mm. Not so for the input Sl1B01901A01A640CDO1A11B011302A610CDO1A1814A26FD8107012AEC
connector, the voltage regu- Sl1B01A805012A03012A01012D1A01A6AFB7114A26FDB6114A26F61BC1
lator, the smoothing capaci- S11801C001B6104CB710A605B1102703CCO1A5CC0127CCO1E4CCO2626C
tor and the buzzer. however. S11801D8010106CCO2F6CC041CCC037B3F101102A680CD025EA601B7F6
which require 1.5 -mm dia. S11B01F000CD02461002A6208700CD0246A620B700CD0246A641B7000A
holes. S11B0208CD0246A66CB700CD0246A66CB700CD0246A675B700CD024622
The connectors for the S11B0220A66DB700CD0246A661B700CD0246A667B700CD0246A665B775
input information and the Sl1B023800CD0246A621B700CD0246CCO4A1A610CD025E12021A01A6D9
supply voltage are PCB S11B025040CD025E1B011302A610CD025E814A26FD813F101102A6801A
mount screw -type terminal S11B0268CDO2CEA601B700CDO2B61002A620B700CDO2B6A620B700CD9C
blocks for a reliable connec- S11B028002B6A644B700CD02B6A645B700CD02B6A646B700CD02B6A68F
tion to the various cables. To S11B029841B700CD02B6A655B700CD02B6A654B700CD02B6A621B700E2
enable it to be mounted Sl1B02B0CD02B6CCO2D2A610CDO2CE12021A01A640CDO2CE1B011302D7
higher than the other com- Sl1B02C8A610CDO2CE814A26FD811801AD071901ADO3CCO2D2AE02CCA5
ponents. the display is con- Sl1B02E002E2A6FFB7121A014A26FBB6121B014A26F25A26ED813F10A7
nected via a couple of Sl1B02F81102A680CD0377A6018700CD035F1002A620B700CD035FA679
stacked turned -pin sockets. S11B031042B700CD035FA672B700CD035FA675B700CD035FA66CB700E1
A pinheader is then carefully S11B0328CD035FA6653700CD035FA675B700CD035FA672B700CD035F9A
soldered directly to the LCD S1180340A620B700CD035FA64FB700CD035FA64BB700CD035FA621B7C5
connections. and inserted S118035800CD035FCCO4A1A610CD037712021A01A640CD03771B011361
into the top socket. S11B037002A610CD0377814A26FD813F101102A680CD0418A601B70034
It is recommended to fas- S11B0388CD04001002A620B700CD0400A642B700CD0400A6728700CD1C
ten the supply reservoir ca- S11B03A00400A675B700CD0400A66CB700CD0400A665B700CD0400A6C7
pacitor on the board by S11B03B875B700CD0400A672B700CD0400A620B700CD0400A62138700B6
means of a nylon strap. The S11B03DOCD0400A620B700CD0400A650B700CD0400A66FB700CD0400D7
current consumption of the S11B03E8A66DB700CD0400A670B700CD0400A665B700CD0400CCO4A1BC
circuit is so low that a Sl1B0400A610CD041812021A01A640CD0418113011302A610CD041881F2
heatsink is not required on S11B04184A26FD813F101102A680CD049DA601B700CD04851002A62058
the voltage regulator. S11B0430B700CD0485A650B700CD0485A66FB700CD0485A66DB700CDE7
Observe the polarity of S11B04480485A6708700CD0485A665B700CD0485A620B700CD0485A65B
the diodes and electrolytic S11B046053B700CD0485A665B700CD0485A675B700CD0485A66CB70017
capacitors. and make sure S11B0478CD0485A665B700CD0485CC04A1A610CD049D12021A01A64050
the motherboard/display as- Sl1B0490CD049D1B011302A610CD049D814A26FD81AEO2CCO4A6A6FF53
sembly is sturdy. Sl1B04A8B7124A26FD1A01B6124A1B0126F25A26EDCCO1A5202020560C
S11B04C06572733A312E312030372D393520422E4C45434C4552432040
Software S10904D82020202020205A
S1040784016F
The control software con- S10507FE0100F4
sists basically of a classic S9030000FC
I/O line handler and a sec-
tion which sends characters
to the LCD. The texts which Fig. 4. Object code to be programmed into the 68705P3 controller.
appear are easily modified to
suit personal requirements.
allowing the circuit to be
modified quite easily for any sion of the first message. ing). except for the audible ticore cable.
other application which re- Next, routines are executed alarm subroutine. which The two screw terminals
quires system status and which define the permissible forms an endless loop. at the far right are con-
alarm messages. setup times of the various Next comes the 'version' nected to the supply voltage
Instructions to keep a signals. Then comes an message. and then the copy- (between 6 and 15 V a.c. or
watchdog asleep appear all input line scanning opera- right notice. At value 678,1, d.c. at about 10 VA). The
over the program. Note, how- tion in order of priority, fol- there is the programming input voltage may be sup-
ever. that no watchdog is im- lowed by a five times over byte of the chip: the MOR, plied by a transformer fitted
plemented in this version of verification of the logic state followed by the rest of the inside the case. a mains
the hardware. That is be- which should be different control program. adaptor. or it may be sup-
cause I had to limit myself to from the 0 V belonging with plied by the boiler's internal
30 components to meet the the non -used half -cycle in Connections power supply.
rules of the Competition. the sinusoidal wave at the The two terminals at the
The software starts by al- inputs. Return to the loop if The connection is made on far left should be connected
locating the ports and their nothing is detected. or jump the terminal strip of the con- to the panel strip in parallel
direction (I or 0). Next, the to the relevant subroutine trol panel. where the thee with the burner motor.
memories are configured. for the message to be writ- 'signals' required for the The two remaining termi-
and the ports are cleared. ten. The subroutine com- monitor are tapped and sent nals are connected to the same
Then follows the display ini- pleted. always return to the to the remote monitoring panel. to the points marked
tialisation and the transmis- main program (input read- unit by a suitably rated mul- 'fault'. 'error' or similar.
ELEKTOR ELECTRONICS JANUARY 1996
62 DESIGN COMPETITION WINNERS
For reasons of security using a simple editor: that is The Competition version of Conclusion
(risk of shunting, or return the reason which prompted the circuit contains less than
currents via other termi- me to equip various subrou- 30 components. For my own Although the application of
nals). it is best not to use a tines with this property. use. I made a version which is the circuit is neither dedi-
common wire. Instead. use The input voltages may be slightly more complex: it has cated nor restricted, the
two wires for each signal to adapted to suit another ap- four inputs and a watchdog. monitor is relatively inex-
be fed to the remote [Link]. simply by shorting The fourth input is connected pensive. based on easily
out C6 and C8 if direct volt- to the ignition transformer. found components. and
Options ages are applied, or by These additions bring the easy to build. (950308)
changing resistors R3. R4 number of parts to 38. which
Obviously it is possible tio and R5 to limit the input is more than allowed by the
modify the display messages current to 15 mA. Competition rules.
(UK)
CONTROLLER 4,
The main feature of the circuit is that it is very easy to switches Si and S2. When torque is about 2 times
S3 (ENA) is set to low, every higher than in half-step
construct. In addition, it has a very low price and is output 05-08 goes low so mode. though in the half-
based on easily obtainable components. Suitable that the driver transistors all step mode the step resolu-
motors can be salvaged, for example, from old 5.25" switch to their off state. The tion is two times better.
internal state counter can The step sequence can be
floppy disk drives. The other components in my project also be reset by pulling up reversed by setting the DIR-
may be found in just about any junk box. By contrast, the RES line with switch S4. input high.
special controller chips are often not so easy to obtain In full -step mode. the motor The binary output table
or are pretty costly.
+7 24V
Design by Sami
Karhulahti
P1
A
+5V
TO
R2
So this simple controller is 7
the answer to this problem. 6
The prototype circuit was
used to control a small mir- TCGG
ror attached to a motor spin- c1 IC2
dle in a light effect unit. DI -4z= R10 01
The heart of the stepper
motor controller is a GAL +5V
16V8 chip, which contains A
the 8 -state counter and +5V
R9 Q2
combinatorial logic required A
S1-4 CI K
to control the driver transis- nip
II
C
tors. A timer chip (555) is re- HALF 3 C2
quired only to generate clock ENA 4 ib R8 Q3
RES 9
pulses and is not required if 6
04
07
13
I/O port. This is why the cir- 12
cuit can be adapted to many 11 ,. J9
purposes where simple and GAL16V8
cheap stepper motor con- IC1
trollers are needed.
The stepping speed can be
adjusted by means of poten-
tiometer P1 and changing
the value of C 1. while the di- 960303-11
rection of rotation or
full/half step mode can be
selected by small DIP Fig. 1. Circuit diagram of the simple stepper motor controller.
4 L H H L 4 L L L H
the controller itself draws R7-10 = 11(fr 0.25W
negligible current. the cur- P1 =1 M12 lirvlog potentiometer
1 H L H L 5 L H L H rent consumption of the
2 Capacitors:
H L L H 6 L H L L whole circuit depends C1,C3 = 10pF 10V electrolytic cap.
3 L H L H- 7 L H H L mainly on the motor type se- C2 = 10pF 50V electrolytic cap.
4 L H H L 8 L L H L lected. (950303)
Semiconductors:
IC1 = GAL16V8, programmed
([Link])'
IC2 = CA555
IC3 = 7805
01-4 = BC337
01-4 = 1f14001
0
0{0 +4'
as
Miscellaneous:
S1-4 = 4 -way DIP switch block
M = unipolar stepper motor 7-24V
equations
GO* A := /A /RES
42F2194*OP20*F0* B := DIR A * B * /RES
L0224 11101111111110111111111111111111*
+ DIR /A /B * /RES
L0384 01011101111110111111111111111111*
L0416 01101110111110111111111111111111* + /DIR * /A * B * /RES
L0448 10101101111110111111111111111111* + /DIR A * /B * /RES
L0480 10011110111110111111111111111111* C t= DIR * /A * /B * /C * /RES
L0576 01101110111010111111111111111111* + DIR * A * C * /RES
L0608 01011111110110111111111111111111* + DIR * B * C * /RES
L0640 01111101110110111111111111111111*
+ /DIR * /B * C * /RES
L0672 10111110110110111111111111111111*
L0704 10101111110110111111111111111111* + /DIR * /A * C * /RES
L0736 10011101111110111111111111111111* + /DIR * A * B * /C * /RES
L1024 11111111111111111111111111111111 Tl = /A * H_F * ENA * /C
L1184 11100111011011111111111111111111* + H_F * /B * ENA * /C
L1216 11110110011011111111111111111111* + /H_F * IS ENA
L1248 11111010011111111111111111111111* [Link] = vcc
L1260 11111111111111111111111111111111*
L1440 11100111010111111111111111111111*
L1472 11110110010111111111111111111111* T2 = /A * H_F * ENA * C
L1504 11111001011111111111111111111111* + H_F * /B RNA * C
L1536 11111111111111111111111111111111* + /H_F * B * ENA
L1664 11100110011011111111111111111111* [Link] = vcc
L1696 11101010011111111111111111111111*
L1728 11011001011111111111111111111111*
L1760 11110101010111111111111111111111* T3 = /A * H_F * /B * ENA /C
L1792 11111111111111111111111111111111* + /A * /H_F * /B * ENA
L1920 11100110010111111111111111111111* + A * /H_F B * ENA
L1952 11101001011111111111111111111111* + H_F * B * ENA * C
L1984 11011010011111111111111111111111* [Link] = vcc
L2016 11110101011011111111111111111111*
L2048 11111111001100010011100100110001*
L2080 00110010001110010011010000110000* T4 = /A H_F * /B * ENA * C
L2112 00110011000111110000000100001111* + /A * /H_F * B * ENA
L2144 00111111000000001000011110000111* + A /H_F * /B * ENA
L2176 100011111000111101* + H_F * B * ENA * /C
C73FE* [Link] = vcc
0000
It is generally known that young children soon develop do is insert the key in a spe- A clean 5-V supply volt-
cial reader, which then age is supplied by a voltage
a habit of watching TV far too long. Although most switches on the TV. The re- regulator consisting of T1,
parents would like to see them reading hooks or maining time is indicated by DI and Ul. The TV Is
playing Quietly, youngsteis will spend hours on end in an LED scale. When the end switched on and off via a
of the scale is reached, the relay. Kl. which is con-
front of the telly if nothing is done about it. time is up. and the TV is trolled via transistor T2. The
switched off without warn- use of a relay ensures a
ing. You, the responsible complete electrical isolation
parent, have a 'master key' of the circuit from the
which enables the user keys mains.
Design by Robert Lacoste to be 'charged' with a certainThe unit is operated by
number of time units. This three push -buttons. SW I.
master key also allows the SW2 and SW3. Four
rightful owner to watch as jumpers. i.1131-JP4, allow dif-
The simple circuit presented ing habits. Of course. the much TV as he/she likes! ferent modes of operation to
here provides an original so- Telly -Guard may be used for be selected, depending on
lution to the above educa- any other application where Circuit description how you would like the unit
tional problem. It allows you electronic time allotment is to function (see below under
to 'give a certain amount of required. The circuit diagram is very 'Practical use'). The 'remain-
TV viewing time to each simple indeed. and based on ing time' indicator is formed
youngster, who is free. in The principle an inexpensive microcon- by an array of ten LEDs (D4).
principle, to use up this time troller. the Motorola Don't worry, the meaning of
as he or she sees lit. After a Each little rascal has a per- MC68705P3. The entire cir- the LED bar is easily learned
short learning phase. you sonal 'key` which 'contains a cuit contains only 30 compo- and understood by children.
will notice (hopefully) that certain number of time nents. including the The unit has two more
the children are developing units. To be able to use the reader/controller and one LEDs. D5 indicates the
much more intelligent view- TV set, all he or she has to key. on/off status of the TV set.
AL
22
s"
anus SW r:s A
aL
it *111001
ILA
sDN
JL Chas I
TOPS WCZTIMCI
-C
560304.11
Fig. 1. Circuit diagram of the Telly -Guard. Translations: terre = earth: moins = down: plus = up: creation clef maitre = create master key;
temps restant = remaining time: haut = high: bas = low: marche = on: mode maitre = master mode: clef (n fois) = key (n times).
PESION, COMPETITIONININNERS5
,
0043101mc
960304.EL1
m MO
1- 0Ligq-
(
a-
R-10 (Y
tr
TELE o ._.-(-- I I
L.1) )
c_miJ (
CL
Oci
LL
_c
U
IY U -Oft
220l)
U-
CND
ru
960304.ES1
Fig. 2. Copper track layout and component mounting plan. Artwork produced with Layo1 E.
S1110100A680B704A6FFB705A6F7B706A600AB
JP1 JP2 JP2 Unit (h/min) Total time S111010EB71233713B714B716B717B718B71947
X X X 4 hours 40 hours S111011CB71AB71BB71CB71DB723A614B71527
X X 2 hours 20 hours s111012AA65013720A61413722A6FFB721A662DE
1 hour 10 hours
S1110138B7081F091D099ACC0142CC01459A53
X X
S11101469BA601B7233D1A270AA600B71ACDBF
X 30 minutes 5 hours S11101540281CC0145B621A1C7220AB621279B
X X 15 minutes 2 hours 30 min. S111016206CD0287CC0178B621A1EE2606CD8B
X 10 minutes 1 hour 40 min. s111017002B5CcO1E3cC01459A9BA602B7234D
X 5 minutes 50 minutes s111017E3D1A270DA600B71ACDO2AECD0281A0
1 minute 10 minutes S111018CCC01453621A100270AA1EE2706A149
S111019AFF27022006CDO2A5CCO1B3CD047cC4
S11101A82606CD0291CC0178CC01789A9BA654
S1100196048723B621A1EE2606CD02B5CC78
S11001C301E3B621A1C7220AB6212706CDOB
51013011300287CC0178CD047C2606CD0c
is not difficult. it does re- ing the 'hidden' push-but- S11101DBO2AEcC0145CCO1B39A9BA603B72318
quire accuracy and a little ton. SW3. A user key is S11101E93D19270DA600B719CDO2BECDO2CDDB
patience. Pay attention to made as follows: insert a S11001F7CCO2393621A1EE2706CDO2C4CCFE
proper isolation between the blank key. press SW3. and S11102040209CCO1E39A98A60513723cD047c26
S11102122606CDO2D6CC0145B621ALEE260665
parts and the metal screen- then SWI ('down'). This pro- 5111022 OCDO2B5CCO1E3B621A1sE270AA1FF61
ing of the plug (which is con- duces a fully charged user 5111022E2706CD02CDCCO239CCO2099A98A63C
nected to +5 V). key. If you leave this key in- S111023C06B723B621A1EE2706A1FP27022054
As with all mains -pow- serted in the reader. the sys- S110024A06CDO2C4CCO209CD047C2606CDED
5111025702D6CC01453D19270DA600B719CDDE
ered circuits, precautions tem starts to count down the 5111026502EFCD02CDCCO2393D18270DA600C4
should be taken to ensure time units until the load is S10F0273B718CDO2DFCDO2CDCCO239CC8F
electrical safety. In particu- switched off. 5111027F0239A6EECD0351811E00A601B7136D
lar. the circuit must be To charge a user key. first s111028DCD048381CD0483B621270C4AA1C77A
S111029132302A6C7B721CD035181A603371FBF
earthed, so that it remains insert the master key (D3 S11102A9A600B71E811F00A600B713811E0019
safe if the transformer or the lights). remove it. an then s11102B7A601B7131371481A6C7CD035181A6C3
relay breaks down. This pre- the user key. Next, adjust S11102C50AB71FA600B71E81A6051371FA60024
caution should always be the number of time units to S11102D3B71E811F00A600B713B71481B62111
S11102E1AB14A1C72302A6C7B721CD035181D8
observed. unless you are be given by means of push- S11102EFB621A0142A06A1C72302A600B72137
dealing with a double -iso- buttons SWI and SW2. S11002FDCD035181100299cD032cA680CDB4
lated device. which is diffi- Other keys are charged in S111030A0339CD0343B710CD0343B7111502D9
cult to produce by a the same way. The reader S11103181102B61143B1102608A1C72306A195
S1110326EE2702A6FF81240414022002150211
hobbyist. Here, the earthing switches to normal mode au- s11103341202130281AE0849CD032C5A26F999
is achieved by connecting tomatically if there is no S111034281AE0812020702004913025A26F582
the +5 V line to the earth pin push-button activity within S1110350813710100299C13032CA630CD0339CD
51110355150211029D9D9D100299CD032CA63F
of the mains plug. Although 10 seconds. S110036C40CD0339B610CD0339B61043CD92
the mains voltage is only Although the construction s11103790339150211029D9D9D10020702FD1D
present at some points at and use of the Telly -Guard S1110387110281010006A600371C2014361C4A
the rear side of the PCB. you should be within reach of S1110395A1FF270E3C1CB61CA1022506A6FFE4
S11103A3B719B71C030006A600B71B2014B63A
must always pull the mains most of you. getting children s11103B11BA1FF270E3C1BB61BA1022506A6AE
plug before doing any work to accept the principle of S11103BFFFB718B71B050006A600B71D2014D3
on the circuit. limited TV viewing time may S11103CDB61DA1FF270E3C1DB61DA10225067C
present some fierce prob- S11103DBA6FFB71AB71D8133173A152606A6DA
S11103E914B715331613612A114241F0C001CF1
Practical use lems initially. (960304) s11103F73D162704A600201413612BB12BB123A
S1110405BB1211B12BB12BB12Bal2BB12B3124A
Fit jumpers JP1. JP2 and Note: the software men- S11104133D172734A1652504A601205Ak151E6
S11104212504A6812052A13D2504A6C1204A2F
JP3 before vou switch on the tioned in this article is avail- S111042FA1292504A6E12042A1152504A6F169
circuit. These jumpers set able on floppy disk, see page S111043D203AA1012504A6F92032A6FD202EA6
the length of a time unit. The 70. S111044BA1B52504A60E201AA1A12504A61E03
total number of time units S11104592012A18D2504A63E200AA1792504B7
S1110467A6752002A6FE3D132702A4F73D1434
which can be charged is ten. 511104752702A4FB13701813D1526023D1F8114
The available options are S1110483B600444444A407A100260AA6D0B73C
shown in a separate box. 511104911FA602B71E205CA104260AA668B7A7
S111049F1FA601B71E204EA102260AA6B4B755
S11104AD1FA600B7152040A106260AA65AB785
Jumper JP4. if fitted. S11104BB1FA600137152032A101260AA62DB7E7
gives a 'magnifyMg' effect S11104C91FA600B7177024A105260AA61EB7F2
during the last time unit. s11104D71FA600B71132016A103260AA6OFB703
When the available time has S11104E51FA600871E2008A603B71FA600B767
S11104F31881A662B7081F0913610B7241361101
dropped to one tenth of the 6111050113725CD03E2CD038A3A202618A65072
total time. the LED scale is S111050FB7203D1E26043D1F270CB61FA00179
'magnified' by ten. and the S111051DB71FB61EA200B71E3A222613A6145C
display starts to flash. This S111052BB722CD0301C70021A1FF2602A600BE
S1110539C700120F0905A601Cc054D3624B764
function is disabled when S111054710B625B711809BC70010A6F2B701AD
JP4 is not fitted. Your S1110555CD0568C60010434848AA01B701CD81
choice! S11105630568CC0551A650B711A6FP4A26FD27
The circuit is adjustment - S10805713A1126F78198
610407840769
free. After taking it into use 510907F804F501000100Fc
for the first time. you should S10507FE0100F4
start by making the 'master S9030000FC
key'. This done by inserting Fig. 4. Object code to be loaded
a blank key. and then press - into the microcontroller.
ELEKTOR ELECTRONICS JANUARY 1996
__DESIGNCOMEEInioN WINNERS 67
SMARTCARD READER
This design answers the widespread interest in Centronics 9
applications involving smartcards. Chip -type O 1 connector -r
telephone cards and credit cards catch the fancy of 0 R3 05+ green
2 03
O 10I
many. Those of you thinking of fraud at this point need O
15
R2
16
D1
7-1 01 I
Cl
DS
red
this design. The circuit is, however, suitable for many D1
18
03
H
D3
19
D4
GND H
DV RI ++ yello...
'ICC
20
8 05
O 0 RESET
21
9 137
CLOCK
22
10 ACK
DATA
23
11 BUSY
0 0 SWITCH
24
O
GND
960310 - 11
PCB Designers
For Windows 3.1, '95 or N
Runs on any PC nu rirg Vindows 31, Windoks 45 or
Wthicurs NT with a mintnurn 2MB RAM
WA work with arty WrKichts supported prtiter and mor 1:-
..0_125_1
COMPONENTS LIST
R1,R2,R3 = 11(05
D1-04 =1N4148
SMART CARD CI = 10oF 16V radial
READER LED1 = 3mm dia.. yellow
LED2 = 3mm dia. red
LED3 = 3mm dia.. green
O
Con1 = Centronics socket. PCB
mount, angled pins.
Con2 = Smartcard reader unit.
1:11../ CLOCK
RESET
DATA
Available from eMedia GmbH,
Postfach 610106. D-30601
D2
. SY ONO OK Hannover. Germany. Price DM 12.
0/=- 0.
4. a
0.I.
40
4.
O
a
a
N -E -X -T M -O -N -T -H
iD-
c, another 16 -page section of
Elektor Electronics devoted to
prize-winning entries from our
0 International Circuit Design
Competition 1995.
A selection from the subjects:
The program is relatively The routine 'my_card' further experiments. you Microcontroller Switching
simple. There are various contains the registration can make it as intelligent Clock RICH
routines for the basic func- number of one of my own and attractive as you like. PC -Driven Battery Tester
tions (LED on/off. clock telephone cards. The num- (960310)
high/low-. etc.). The main ber may be replaced with 'Green power' for PCs
program first checks if a your own number. The green Note: the software men- Hybrid Headphones Amplifier
card is inserted ('switch'). If LED will light when this tioned in this article is avail- - Intelligent Motor Control for
so. data are read using the number matches that on the able on floppy disk. see page WC Models
ATR (see Ref. 1),and card. If the numbers are dif- 70.
checked. If this information ferent. the red LED lights. Reference: PWM Signal Generator
is okay. it is converted into The program is only in- 1. Chip Cards. Elektor Don't miss the February 1996 Issue!
legible text. tended as a starting point for Electronics April 1995.
ELEKTOR ELECTRONICS JANUARY 1996
Please mention ELEKTOR ELECTRONICS when contacting advertisers 75
Pico Releases PC
Potential
Pico's Virtual Instrumentation enable you to use your
computer as a variety of useful test and measurement
1152/m__--.
i 1
PicoScope
'Virtual
instrument'
software.
TC-08 199
TC-08 + Calibration Certificate £ 224
complete with PicoLog. software drivers and connecting cable.
range of thermocouple probes is available.
/
Voltmeter
.54,1- 16 E 219 The ADC -100 offers both a high
sampling rate (100kHz) and a high
s fie
/ ,S,-Cdth software. . power349 resolution. It is ideal as a general
supply and cables purpose test instrument either in the
lab or in the field. Flexible input ranges
(±200mV to 20V) allows the unit to
connect directly to a wide variety of signals.
"412,e-100 with PicoScope £199
"nye- /0 with PicoScope & PicoLog £219
1 Channel 8 bit
Lowest cost in the Pico range The ADC -10 gives your computer a single channel of
Up to 22kHz sampling analog input. Simply plug into the parallel port.
0 -5V input range pilDe-- /0 with PicoScope £49
Carriage UK free. Overseas £9 Oscilloscope Probes ( x1. x10 1 £10 PicoScope & PicoLog £5_9A
=Pico Technology Ltd. Broadway House. 149-151 St Neots Rd, Hardwick, Cambridge. CB3 70J
Tel: (0)1954 - 211716 Fax: (0)1954 - 211880 E-mail: 100073.2365 @[Link]
Phone or FAX for sales, ordering information, data sheets, technical support. All prices exclusive of VAT
RIB
INNI clo
O 3 = 1001AV
4 = 10pAN
D3
715h 8066 :005
100n R19 Re2
IC2 1114148
100.
3 ICI -1
- S3 Re3
R20 2I
TL081 S2 1 = 10V 1600
13
I
2 2 = 5V L165V
3 = 2V
4 = 1V
j 1 I
3
R24
Fi71-0
R5 IR5 IR7 IRS _1 R25
5 = 055
Cs 100k
MIM 6 = OV2 D2
;7.
100n
.-01 15V
1110 15V 11441411
O
O 1060
R9 DI
1N4148
1N4148
SIb
RIO
11!
IF111
9
I- 5 15V
1126
C6
R13
IS 111-.. 100n 1771.
Oii C7
0-5
OUT
91c 10n IN4148
12
H IM
Fl
TRI
Ce
In 0 IN-°
IC3 = TL082 x- scope
D7 D5 IC4 15V
015v R27 K1
7815
010
1100 o(:)0
DO DB R31
= ... N NE
T ..
C13 C15 C17
7-1 - R33
Tn Re9 V' scope
2z 15V
4VA5
4x 11/4004 1"GP
25V IGDn 1060 R32 K2
R25
C14 C16 cia 15)0
BM -
10005 100n
Min
105
25V 0 1130
16V
7915
015V 500032 - 12
IC5
Integrated Circuits:
ICI = TL081
0 IC2 = L165V
1C3 = TL082
to IC4 = 7815
01 R30 10
105 = 7915
0 1 R28 1 00000000
01 R29 10
Miscellaneous:
01 R31 10
O0 K1. = 13NC socket
Cl R32 10° K3 = 2 -way terminal strip.
r 0) 27 10
pitch 7.5 mm
0-0110 Of R25
S1 = rotary switch. 3 -pole, 4 -position
011 04 i00 52. S3 = rotary switch. 1 -pole. 12 -posi-
01 05 11100
tion (see text)
01 R26 100
S4 = mains on/off switch
Tr1 = mains transformer, two secon-
Measuring with Lissajous figures This corresponds to an ellipse. When a = b. that is, when
The measurement technology used depends on Lissajous the impedance is a pure reactance, the ellipse becomes a
figures. These are plane curves formed by the composi- circle.
tion of two sinusoidal waveforms in perpendicular direc- The ellipse is composed of:
tions. that is, they form a coordinate x -y system. In such x (tot) = U1 sin (tot)
a system. the displacement of a point is determined by and
the vector sum of the x and y values. y (tot) = 1.19 sin ((at + p).
where p is the phase shift, whose value is determined by
sin -1 (Mot =0))/(Ymas).
where y)",..0) is the intersection of the ellipsewith the y-axis.
Figure A2 shows an example of an ellipse and indi-
cates at which two points the measured values are found.
Impedance Z of the c.o.t. is determined simply by divid-
ing the peak values of the two voltages (y into x) that are
applied to the oscilloscope:
Z=1.11/U2 S.
where S is the transfer factor of the current sensor in A
V-1. In the present tester, this factor is set with S3.
Both the reactance and resistance can be derived from
the impedance. For instance. in case of a series network
of a resistor and a non -ideal inductance:
Rs = Z cos p
and
Xs = Z sin p.
In case of a parallel network of a resistor and a non -Ideal
capacitor:
R = Z cos p
UCCZ111 - I and
X = Z sin p.
daries. 15 V. 4.5 VA each (for in- from Dau Ltd, telephone (01243)
stance. Velleman 2150050M from 553 031
Maplin) 1 off enclosure. 60x150x132 mm
F1 = fuseholder (preferably integral in (23/sx57/ff,x53/16 in)
mains entry) with 50 mA slow fuse 1 off PCB Order no. 960032 (see p.70)
1 off heat sink for IC2. 20 K W-1. for (960032)
instance. Fischer FK222/SA-220
ELEKTOR ELECTRONICS JANUARY 1996
80
'l+1G21 It
OW INTERACT E
IS YOUR
ULTIboard, one of the leading PC based design
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ULTImate Technology offices & distributors. tiro
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10
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wen fuled with copper of the desired mteiligient router uses copper slating processed to mune p
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and tracks. hard:* Lp to 32 twee as weg ea
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41: 4
44-(0)1203-233-216
-or
ft
:O:JOZ
Robinson Marshall (Europe) Plc
rirva.
::tra.'" t1I: A
mrankr2-5193933 91221151-453-5583 Cy/x=242-1068 atom& 33-2i0109 finbmt 0.25r-5033 Franck- l+ooi-txtoO0 Gemtarry:71162:740 Greeee:1-5249981
Hurway 1-2.1500412 India: I I.5444343 Eziel 3-647-5613 ItalF 1.1-137A549 must:3-33813136 Malian[ W3-7778945 Melia' 5-3563075 Netherlands 18031-7666
New Amilanct9-ai7-1-56 Norv.w. 22-16-70-45 !taut* 143146609 Rrnuporc 46-2-0006 gmenia 6141-4i:it, south Africa 33168309 South Koita:2.2-222-3431
Spain' :1-553-3234 Sri lankw144(3,197D Surderi:/3-7495$0011nalantb66249136952 United KingdormN3-2A-3216