The humble Synchronous Buck Converter
- - - - and how it becomes the root of all my digital control loop design - - - -
By: Arief Noor Rahman
INTRODUCTION
Synchronous Buck (SR-Buck) is one of the basic converter structures together with boost and buck-boost converter.
Despite of it being a very basic converter, with some little hindsight we can extend the controller structure explained in
this article for so many converter control design. So far, I have managed to use the principle for:
1. Single SR-Buck
2. Multiphase SR-Buck
3. Totem Pole PFC
4. Three Phase 6 switches PFC
5. Phase shift full bridge (CC/CV charger)
6. Induction motor drive (torque and speed regulation)
Before moving forward, there are a few design parameters and characteristics that I always have:
1. Controller is based on average current mode control
Overall, current mode control is generally considered to have overall performance over voltage mode control. Such
as, ease of tuning, better stability, better protection scheme. However, the nature of digital control with constant
periodic sampling position makes peak current mode control (PCMC) to be impossible to be implemented and force
the design of such controller to adopt average current mode control (ACMC). Compared to analog PCMC, digital ACMC
has more accurate current regulation and protection however it unfortunately has much lower voltage loop
bandwidth (~10x lower) due to (1) cascaded control structure and (2) higher phase loss from sampling delay.
𝐹𝑠𝑤 𝐹𝑠𝑤
2. Current loop bandwidth is typically set at and Voltage loop bandwidth is set at
20 100
Both analog and digital PWM controller inherently has delay due to the PWM modulation, so called PWM transfer
𝑇𝑠𝑤
delay which amounted to 2
. However, digital PWM controller has an additional delay due to the sampling and
computation time requirement to complete the control algorithm. This extra delay on digital PWM controller resulting
𝐹𝑠𝑤 𝐹𝑠𝑤
in the lower attainable crossover frequency of the inner loop to be around 20
(compared to 10
when analog
controller is used). The outer loop crossover frequency is selected at 20% of the inner loop crossover frequency.
SYSTEM MODELING
Figure 1. Synchronous buck circuit schematic
To design the controller, first step is to convert the circuit schematic in Fig. 1 into a control loop block diagram that includes
the system model and controller model as in Fig. 2. Average current control mode is shown in this diagram which formed
cascaded control loop with voltage control loop on the outer loop and current control loop on the inner loop. To ensure
high modeling accuracy, it is necessary to include as much detail as possible such as all the (1) sampling and PWM delay,
(2) system gain, (3) feedback circuit, and (4) output filter if exist, although input filter is not typically included for analytical
derivation for being overly complicated.
Figure 2. Synchronous Buck controller and circuit model diagram
On the system modeling, the circuit can be modeled into simple current model and voltage model. The current model is
simply the inverse impedance of the inductor. Meanwhile, the voltage model can be selected from two options: (1) is
when load is assumed to be completely arbitrary or (2) when load is assumed to be resistive. In most literature, resistive
load at maximum load is often used to describe the voltage model for controller design purpose. However, I personally
prefer to use the arbitrary load model for my controller design.
System delay in digital PWM controller comprised of two different kinds of delay, (1) the inherent PWM transfer delay
with duration of 0.5𝑇𝑠𝑤 and (2) sampling delay. Sampling delay also called computation delay is the delay caused by the
required computation time to calculate all the necessary control algorithm. The duration of sampling delay is rounded up
to the nearest integer multiply of the switching frequency. In total, the system delay is equal to the sum of both delays
which is (𝑁 + 0.5) × 𝑇𝑠𝑤 , 𝑁 ∈ {0, 1, 2, … }. From the higher delay, it reflects on the higher phase drop which causes
decrease maximum attainable crossover frequency for the desired phase margin (> 40°, or my preference is 60°). Thus,
𝐹𝑠𝑤
in digital controller, the rule-of-thumb for crossover frequency is at 20
.
Finally, the gains (controller and PWM gains). The PWM gain described the correlation between the PWM duty cycle and
the average switch node voltage, ̅̅̅̅
𝑉𝑠𝑤 . Due to the existence of PWM gain, controller gain is simply added to cancel out the
PWM duty cycle. By doing the canceling all the controller design can be performed in the origin voltage and current unit
as in volt and ampere (to me, it is more intuitive although not necessary).
Table 1. Description of block diagram in Figure 2
Voltage model, 𝐺𝑣 (𝑠) 1 1
𝐺𝑣 (𝑠) = ( + 𝑅𝑐1 ) ∥ ( + 𝑅𝑐2 ) ∥ 𝑅𝑙𝑜𝑎𝑑
𝑠𝐶1 𝑠𝐶2
Used when the load is assumed to be
resistive load.
1 1
𝐺𝑣 (𝑠) = ( + 𝑅𝑐1 ) ∥ ( + 𝑅𝑐2 )
𝑠𝐶1 𝑠𝐶2
Used when the load is assumed to be
completely arbitrary load or
controlled/constant current load. In
general, I prefer to use this model
Current model, 𝐺𝑖 (𝑠) 1
𝐺𝑖 (𝑠) =
𝑠𝐿 + 𝑅𝐿
Voltage controller, 𝐶𝑣 (𝑠) Type I Typically, only used for PFC
𝐾𝑣
𝐶𝑣 (𝑠) =
𝑠
PI Controller
𝐾𝑣 (𝑠 + 𝑧𝑣 )
𝐶𝑣 (𝑠) =
𝑠
𝜔
Type II 𝜔𝑝𝑣 is commonly located at 2𝑠𝑤 or can
𝐾𝑣 (𝑠 + 𝑧𝑣 ) be placed at lower frequency as
𝐶𝑣 (𝑠) =
𝑠 necessary
𝑠( + 1)
𝜔𝑝𝑣
Current controller, 𝐶𝑖 (𝑠) PI Controller
𝐾𝑖 (𝑠 + 𝑧𝑖 )
𝐶𝑖 (𝑠) =
𝑠
𝜔
Type II 𝜔𝑝𝑖 is commonly located at 2𝑠𝑤 or can
𝐾𝑖 (𝑠 + 𝑧𝑖 ) be placed at lower frequency as
𝐶𝑖 (𝑠) =
𝑠 necessary
𝑠 (𝜔 + 1)
𝑝𝑖
Controller gain, 𝐾𝐶 𝑇𝐵𝑃𝑅𝐷
𝐾𝐶 =
𝑉𝑖𝑛
PWM gain, 𝐾𝑝𝑤𝑚 𝑉𝑖𝑛 TBPRD is pwm peak counter value as
𝐾𝑝𝑤𝑚 =
𝑇𝐵𝑃𝑅𝐷 specified in TI C2000 family
Voltage feedback ckt, 𝐻𝑣 (𝑠) 𝑒 −𝑠𝑇𝑣 As a common feedback simplification,
𝐻𝑣 (𝑠) = 𝑠 first order plus time delay is used.
𝜔𝑣 + 1 Different kind of filter transfer
Current feedback ckt, 𝐻𝑖 (𝑠) 𝑒 −𝑠𝑇𝑖 function or higher order filter can also
𝐻𝑖 (𝑠) = 𝑠
+1 be used
𝜔𝑖
Sampling and PWM delay, 𝐷(𝑠) 𝐷(𝑠) = 𝑒 −𝑠(𝑁+0.5)𝑇𝑠𝑤
PWM gain, 𝐾𝑝𝑤𝑚 (𝑠) 𝑉𝑖𝑛 TBPRD is pwm peak counter value as
𝐾𝑝𝑤𝑚 =
𝑇𝐵𝑃𝑅𝐷 specified in TI C2000 family
CONTROLLER TUNING – INNER LOOP
The inner loop of SR-buck is depicted in Fig. 3(a) with the simplified version for controller tuning model depicted in Fig.
3(b). Compared to Fig. 2, the controller and PWM gains are excluded as its perfectly canceled out. In the simplified model,
the node Vo is removed as it becomes negligible with much slower dynamic compared to ̅̅̅̅ 𝑉𝑠𝑤 .
(a)
(b)
FIGURE 3. (a) Inner loop detailed model and (b) simplified open loop inner loop model.
𝐼𝐿(𝑓𝑏) (𝑠)
𝑂𝐿𝑇𝐹𝑖 = = 𝐶𝑖 (𝑠)𝐷(𝑠)𝐺𝑖 (𝑠)𝐻𝑖 (𝑠)
𝐼𝐿∗ (𝑠)
Assuming 𝐶𝑖 (𝑠) uses PI controller, the gain of the PI controller can be calculated as following:
1. Determine the target crossover frequency (𝜔𝑐(𝑖) ) and target phase margin(𝜙𝑚(𝑖) ).
2. Calculate the required phase of controller zero (𝜙𝑏𝑜𝑜𝑠𝑡(𝑖) ) at the target crossover frequency
1
𝜙𝑏𝑜𝑜𝑠𝑡(𝑖) = −180 + 𝜙𝑚(𝑖) − 𝑎𝑟𝑔𝑠 (𝑗𝜔 × 𝐷(𝑗𝜔𝑐(𝑖) )𝐺𝑖 (𝑗𝜔𝑐(𝑖) )𝐻𝑖 (𝑗𝜔𝑐(𝑖) ))
𝑐(𝑖)
Note : maximum theoretical attainable 𝜙𝑏𝑜𝑜𝑠𝑡(𝑖) of a PI controller is 90 °, if the resulting 𝜙𝑏𝑜𝑜𝑠𝑡(𝑖) is greater
than 90°, thus lower target 𝜙𝑚(𝑖) or 𝜔𝑐(𝑖) can be selected. For safety margin, I limit 𝜙𝑏𝑜𝑜𝑠𝑡(𝑖) < 85°
3. Calculate controller zero (𝑧𝑖 )
𝜔𝑐(𝑖)
𝑧𝑖 = −1
tan (𝜙𝑏𝑜𝑜𝑠𝑡(𝑖) )
4. Calculate controller gain (𝐾𝑖 )
−1
𝑗𝜔𝑐(𝑖) + 𝑧𝑖
𝐾𝑖 = (abs ( × 𝐺𝑖 (𝑗𝜔𝑐(𝑖) )𝐻𝑖 (𝑗𝜔𝑐(𝑖) ))) → 𝐾𝑝(𝑖) = 𝐾𝑖 and 𝐾𝑖(𝑖) = 𝐾𝑖 𝑧𝑖
𝑗𝜔𝑐(𝑖)
CONTROLLER TUNING – OUTER LOOP
The outer loop model is depicted in Fig. 2 which the open loop transfer function is shown in Fig. 4(a). Detailed model is
necessary for controller tuning design when maximum output crossover frequency is desired. For application where the
outer loop crossover frequency is significantly lower than inner loop crossover frequency, probably 𝜔𝑐(𝑣) < 5% . 𝜔𝑐(𝑖) ,
then the simplified open loop model can also be used. Due to the cascaded controller structure, the outer loop crossover
frequency must be lower than inner loop crossover to avoid oscillation between inner and outer loop (which I typically
limit to 20% . 𝜔𝑐(𝑖) or 25% . 𝜔𝑐(𝑖) ).
(a)
(b)
FIGURE 4. Open loop model of the outer voltage loop (a) detailed model and (b) simplified model
𝑉𝑜(𝑓𝑏) 𝐶𝑣 (𝑠)𝐶𝑖 (𝑠)𝐷(𝑠)𝐺𝑖 (𝑠)𝐺𝑣 (𝑠)𝐻𝑣 (𝑠)
𝑂𝐿𝑇𝐹𝑣(𝑑𝑒𝑡𝑎𝑖𝑙) = =
𝑉𝑜 1 + 𝐻𝑖 (𝑠)𝐶𝑖 (𝑠)𝐷(𝑠)𝐺𝑖 (𝑠) + 𝐺𝑖 (𝑠)𝐺𝑣 (𝑠)
𝑉𝑜(𝑓𝑏)
𝑂𝐿𝑇𝐹𝑣(𝑠𝑖𝑚𝑝𝑙𝑖𝑓𝑖𝑒𝑑) = = 𝐶𝑣 (𝑠)𝐺𝑣 (𝑠)𝐻𝑣 (𝑠)
𝑉𝑜
Assuming 𝐶𝑣 (𝑠) uses PI controller, the gain of the PI controller can be calculated as following:
1. Determine the target crossover frequency (𝜔𝑐(𝑣) ) and target phase margin(𝜙𝑚(𝑣) ).
2. Calculate the required phase of controller zero (𝜙𝑏𝑜𝑜𝑠𝑡(𝑣) ) at the target crossover frequency
3.
1 𝐶𝑖 (𝑠)𝐷(𝑠)𝐺𝑖 (𝑠)𝐺𝑣 (𝑠)𝐻𝑣 (𝑠)
𝜙𝑏𝑜𝑜𝑠𝑡(𝑣) = −180 + 𝜙𝑚(𝑣) − 𝑎𝑟𝑔𝑠 ( × )
𝑗𝜔𝑐(𝑣) 1 + 𝐻𝑖 (𝑠)𝐶𝑖 (𝑠)𝐷(𝑠)𝐺𝑖 (𝑠) + 𝐺𝑖 (𝑠)𝐺𝑣 (𝑠)
Or
1
𝜙𝑏𝑜𝑜𝑠𝑡(𝑣) = −180 + 𝜙𝑚(𝑣) − 𝑎𝑟𝑔𝑠 ( × 𝐺𝑣 (𝑠)𝐻𝑣 (𝑠))
𝑗𝜔𝑐(𝑣)
Note : maximum theoretical attainable 𝜙𝑏𝑜𝑜𝑠𝑡(𝑣) of a PI controller is 90 °, if the resulting 𝜙𝑏𝑜𝑜𝑠𝑡(𝑣) is greater
than 90°, thus lower target 𝜙𝑚(𝑣) or 𝜔𝑐(𝑣) can be selected. For safety margin, I limit 𝜙𝑏𝑜𝑜𝑠𝑡(𝑣) < 85°
4. Calculate controller zero (𝑧𝑣 )
𝜔𝑐(𝑣)
𝑧𝑣 =
tan−1(𝜙𝑏𝑜𝑜𝑠𝑡(𝑣) )
5. Calculate controller gain (𝐾𝑣 )
−1
𝑗𝜔𝑐(𝑣) + 𝑧𝑣
𝐾𝑣 = (abs ( × 𝐺𝑣 (𝑗𝜔𝑐(𝑣) )𝐻𝑣 (𝑗𝜔𝑐(𝑣) ))) → 𝐾𝑝(𝑣) = 𝐾𝑣 and 𝐾𝑖(𝑣) = 𝐾𝑣 𝑧𝑣
𝑗𝜔𝑐(𝑣)
DISCUSSION ON VOLTAGE MODEL
Assuming the same schematic diagram as in Fig. 1 with following component values:
R1 = 0.002Ω, C1 = 1uF, R2 = 0.5Ω, C2 = 330uF, Rload = 10Ω
f = logspace(0.1, 5, 51);
w = 2*pi*f;
Zc1 = 1./(1j*w*1000e-9) + 0.002;
Zc2 = 1./(1j*w*330e-6) + 0.5;
Rload = 100^2/1000;
subplot(2,1,1)
semilogx(f,20*log10(abs(1./(1./Zc1 + 1./Zc2))))
hold on
semilogx(f,20*log10(abs(1./(1./Zc1 + 1./Zc2 + 1./Rload))))
semilogx(f,20*log10(abs(1./(1./Zc1 + 1./Zc2 + 1./2./Rload))))
semilogx(f,20*log10(abs(1./(1./Zc1 + 1./Zc2 + 1./4./Rload))))
semilogx(f,20*log10(abs(1./(1./Zc1 + 1./Zc2 + 1./8./Rload))))
hold off
legend('Cmodel', '100% Rload', '50% Rload', '25% Rload', '12.5% Rload')
xlabel('Freq (Hz)')
ylabel('Z(dB)')
subplot(2,1,2)
semilogx(f,180/pi*(arg(1./(1./Zc1 + 1./Zc2))))
hold on
semilogx(f,180/pi*(arg(1./(1./Zc1 + 1./Zc2 + 1./Rload))))
semilogx(f,180/pi*(arg(1./(1./Zc1 + 1./Zc2 + 1./2./Rload))))
semilogx(f,180/pi*(arg(1./(1./Zc1 + 1./Zc2 + 1./4./Rload))))
semilogx(f,180/pi*(arg(1./(1./Zc1 + 1./Zc2 + 1./8./Rload))))
hold off
xlabel('Freq (Hz)')
ylabel('Phase (deg)')
Note: everything in this statement is purely my own opinion
From a quick observation, it seems like the difference between Cmodel only and RC model at full load and partial load
only exist at relatively low frequency while the high frequency behavior all model are similar.
My opinions are:
1. For controller that is designed for high 𝜔𝑐(𝑣) , the selection of which voltage model should has limited or negligible
effect.
2. Meanwhile, for application with low 𝜔𝑐(𝑣) (<100Hz such as in PFC DC link controller) the selection of the voltage
model will resulting in very different controller gain, with Cmodel only being the preferred choice. The benefit of
such model for design is the resulting controller behavior will behave as such:
a. The gain tends to decrease at the higher 𝑅𝑙𝑜𝑎𝑑 , thus potentially avoiding the resonant peaking across the load
range, when the controller is defined at the highest gain condition.
b. The phase margin tends to increase at the higher 𝑅𝑙𝑜𝑎𝑑 , thus ensuring stability across the whole load range
