EXPERIMENT Nt ia Verification and interpretation of truth tables for AND, OR, NOT, NAND, NOR Exclusive OR (EX-OR), Exclusive NOR (EX-NOR) Gates. Apparatus: Logic trainer kit, logic gates / ICs, wires. Theory: Logic gates are electronic circuits which perform logical functions on one or more inputs to produce one output. There are seven logic gates. When all the input combinations of a logic gate are written in a series and their corresponding outputs written along them, then this. input/ output combination is called Truth Table. Various gates and their working is explained here. AND Gate AND gate produces an output as 1, when all its inputs are 1; otherwise the output is 0. This gate can have minimum 2 inputs but output is always one. Its output is 0 when any input is 0. Truth Table B A Q Ao 0 0 0 o |e) “a ? : ie 2-input AND Digital Logic Gate 1 0 0 1 1 1 Boolean Expression Q = A.B Read as A AND B gives Q OR Gate OR gate produces an output as 1, when any or all its inputs are 1; otherwise the output is 0. This gate can have minimum 2 inputs but output is always one. Its output is 0 when all input are 0. symbol ‘Truth Table B A Q é —2>~ 0 1 1 C 1 0 1 1 1 1 Boolean Expression Q= A+B i Read as A OR B gives Q Scanned with CamScannerNOT Gate NOT gate produces the complement of its input. This gate is also called an INVERTER. It Aas has one input and one output. Its output is 0 when input is 1 and output is 1 when input is Symbol Truth Table A Q A Q 0 1 1 0 Boolean Expression Q= not A or A Read as inverse of A gives Q NAND Gate NAND gate is actually a series of AND gate with NOT gate. If' we connect the output of an AND gate to the input of a NOT gate, this combination will work as NOT-AND or NAND gate. Its output is 1 when any or all inputs are 0, otherwise output is 1. Symbol Truth Table B A Q 0 0 1 Ao— & Q 0 1 1 8 1 0 1 1 1 0 Boolean Expression Q=A.8 Read as A AND B gives NOT Q NOR Gate NOR gate is actually a series of OR gate with NOT gate. If we connect the output of an OR gate to the input of a NOT gate, this combination will work as NOT-OR or NOR gate. Its output is 0 when any or all inputs are 1, otherwise output is 1. Symbol Truth Table B A Q 0 0 1 A a ae Q 0 1 0 eC 1 0 0 1 1 0 Boolean Expression Q= A+B. Read as A OR B gives NOT Q Scanned with CamScannerExclusive OR (X-OR) Gate X-OR gate produces an output as 1, when number of 1's a its inputs is odd, otherwise output is 0. Ithas two inputs and one output. Symbol Truth Table B A Q A 0 0 0 B Q 0 1 1 1 0 1 1 1 0 Boolean ExpressionQ=A B Read as A OR B but not BOTH gives Q (odd) Exclusive NOR (X-NOR) Gate ; X-NOR gate produces an output as 1, when number of 1's at its inputs is not odd, otherwise output is 0. It has two inputs and one output, Symbol Truth Table Q > -Hoow 1 0 0 1 HonoDp Boolean Expression Q=A B Read if A AND B the SAME gives Q (even) Procedu 1. Connect the trainer kit to ac power supply. 2. Connect the inputs of any one logic gate to the logic sources and its output to the logic indicator. . Apply varous input combinations and observe output for each one. Verify the truth table for each input/ output combination. Repeat the process for all other logic gates. . Switch off the ac power supply. auaw Result:- verification of all the gates have done successfully. Scanned with CamScannerEXPERIMENT 2 AIM: Implementation of the Given Boolean Function using Logic Gates in Both Sop and Pos Forms. THEORETICAL CONCEPT:- Karnaugh maps are the most extensively used tool for simplification of Boolean functions. It is mostly used for functions having up to six variables beyond which it becomes very cumbersome. In an n-variable K-map there are 2" cells. Each cell Corresponds to one of the combination of n variable, since there are 2" combinations of n variables, Gray code has been used for the identification of cells. Example- Sop; 1/74B+de +80 POS: ¥=(4+BX4+CXB+C) EXPERIMENTAL SET UP:- SOP form POS FORM. SPECIFICATION OF APPARATUS USED:- Power Supply, Digital Trainer, IC’s (7404, 7408,7432) Connecting leads. Scanned with CamScanner(a) With given equation in SOP/POS forms first of all draw a Kmap. (b) Enter the values of the O/P variable in each cell corresponding to its Min/Max term. (©) Make group of adjacent ones. (d) From group write the minimized equation. (©) Design the ckt. of minimized equation & verify the truth table. PRECAUTIONS: 1) Make the connections according to the IC pin diagram. 2) The connections should be tight. . 3) The Vee and ground should be applied carefully at the specified pin only. RESULT AND COMMENTS:-Implementation of SOP and POS form is obtained with AND and OR gates. Scanned with CamScannerEXPERIMENT NO:3 To verify the truth table of OR, AND, NOR, Ex-OR, Ex-NOR realized using NAND & NOR gates. Apparatus: Logic trainer kit, logic gates / ICs, wires Theor NAND gate is actually a combination of two logic gates: AND gate followed by NOT gate. So its output is complement of the output of an AND gate. This gate can have minimum two inputs, output is always one. By using only NAND gates, we can realize all logic functions: AND, OR, NOT, X-OR, X-NOR, NOR. So this gate is also called universal gate. NOR gate is actually a combination of two logic gates: OR gate followed by NOT gate. So its output is complement of the output of an OR gate, This gate can have minimum two inputs, output is always one. By using only NOR gates, we can realize all logic functions: AND, OR, NOT, X-OR, X-NOR, NAND. So this gate is also called universal gate. NAND gates as NOT gate A NOT produces complement of the input. It can have only one input, tie the inputs of a NAND gate together. Now it will work as a NOT gate. Its output is, Y=(AAy NOT (inverter) NAND gates as AND gate A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted, overall output will be that of an AND gate. Y=((AB)Y’ Scanned with CamScannerNAND gates as OR gate "rom DeMorgan’s theorems: (A.B) = A* + BY 7 (A.B =A" +BY =A+B So. give the inverted inputs toa NAND gate, obtain OR operation at output. (A'B’Y =At+B NAND gates as X-OR gate ‘The output of a to input X-OR gate is shown by: Y = A’B + AB’. This can be achieved with the logic diagram shown in the left side, (A(AB)")" B (AByBY X-OR Gate No. Inputs Output 1 AB (ABY 2 A, (ABY’ (A (AB) 3 (AB), B (B(AB)Y 4 (A (AB)’)’, (B (AB)’)’ A’B + AB’ Ne Jow the ouput from gate no, 4 is the overall output of the configuration. Yo = (A(AByY BABYYY (A(ABY'Y" + (B(AB)') (A(AB)’) + (B(AB)’) (A(A’ + BY") + (B(A’ + BY) (AA’ + AB’) + (BA’ + BB’) (0+ AB" +BA*+0) AB'+BA‘ AB’ +A'B een nan Scanned with CamScannerNAND gates as X-NOR gate X-NOR gate i tually X-OR gate followed by NOT gate. So give the output of X-OR gate toa NOT gate. o I ouput is that ofan X-NOR gate Y=AB+ AB" NAND gates as NOR gate ANOR gate is an OR gate followed by N ‘OT gate. So connect the output of OR gate toa NOT gate, overall output is that of a NOR gate. Y=(A+By A 4’ (A + B) (A + BY B a NOR gates as NOT gate A NOT produces complement of the input, gate together. Now it will work as a NOT g, Y=(A+Ay’ = Y=(Ay It can have only one in put, tie the inputs of a NOR ate. Its output is Scanned with CamScannerNOR gates as OR gate A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted, overall output will be that of an OR g: wate _ =((AtBy) = ¥ = (A+B) (A+B). B OR NOR gates as AND gate From DeMorgan’s theorems: (A+B)’ = A” Bs > (A’+B’y = AB” = AB So, give the inverted inputs to a NOR gate, obtain AND operation at output. A (a'+B'y NOR gates as X-NOR gate ‘The output of a two input X-NOR gate is shown by: Y= AB + A’B’. This can be achieved with the logic diagram shown in the left side. ) > (A+(A+B)')' A eat °B+(AtB) X-NOR ae Gate No. Inputs Output 1 AB (A+By 2 A,(A+BY (A+ (AsBy'Y’ Scanned with CamScanner(A+ BY B (A+A+BYY. B+ (AnByy (B+(AsBy'y AB+A’B? Now the o uput from gate no. dis the overall output of the configuration. Y X-OR gate is actually X-NOR a NOT gate, overall ouput is th De noone oe ((A + (A+B)’Y (B+( A+ByY')” (A+(AtBYY".(BHASBY)” (A+(A+B)’).(B+(A+B)") (A+A’B’).(B+A’B") (A + A’)(A + B’).(B+A’)(B+B’) 1(A+B’).B+A’).1 (A+B). (B+A’) AB + A’) +B’(B+A’) AB + AA’ +B'B+B"A’ AB+0+0+BA’ AB+B’A’ AB+A’B’ NOR gates as X-OR gate Bate followed by NOT gate. So give the output of X-NOR gate to at of an X-OR gate. Y=A’B+ AB’ pi (B+(A+B)" Scanned with CamScannerNOR gates as NAND gate ANAND gate is an AND IoT ate fc NOT gate, overall output eee by poy gate. So connect the output of AND gate toa Y= (AByY A A AB (ABY B B’ NAND Connect the trainer kit to ac power supply. : Connect the NAND gates for any of the logic functions to be realised. Connect the inputs of first stage to logic sources and output of the last gate to logic indicator. Apply various input combinations and observe output for each one. Verify the truth table for each input/ output combination. Repeat the process for all logic functions... Connect the NOR gates for any of the logic functions to be realised. Connect the inputs of first stage to logic sources and output of the last gate to logic indicator. 9. Apply varous input combinations and observe output for each one. 10. Verify the tructh table for each input/ output combination. 11. Repeat the process for all logic functions. 12. Switch off the ac power supply. PIAKAMP Result:- Scanned with CamScannerExperiment No. 4(A) To realize Half adder/ Subtractor & Full Adder/ Subtractor using NAND & NOR gates and to verify their truth tables. COMPONE REQUIRED IC Trainer kit, IC 7400, IC 7486 PRINCIPLE The simplest binary adder is called half adder. Half adder has two input bit Oneoutput bit is the sum and the other is the carry. They are represented by in logic symbol. and two output bits. and ‘C° respectively The simplest binary subtractor is called half Subtractor. It has two input bits and two output bits. One output bit is the Difference and the other is borrowed. They are represented by ‘D’ and ‘8’ respectively in logic symbol. Truth table of Half Adder ‘Truth table of Half Subtractor Inputs Output Inputs Output A B s c A B D BOR 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 1 0 0 Scanned with CamScannerA A B s s Cc B Logic circuit of Half adder and Haff adder using NAND gate only A A 8 DIFF D Borrow 8 BOR Logic circuit of half subtractor and half subtractor using NAND ga! PROCEDURE: 1. Verify whether all the wires and components are in good condition 2, Set up a half adder circuit and feed all the input combinations 3 Observe the output corresponding to input combinations and enter it in the Truth table 4, Repeat the above steps for half subtractor circuits. RESULT: Half adder and the half subtractor circuits are set up using logic gates and verified the result. Scanned with CamScanner. : Experiment No. 4(B) Vo realize Half adder/ Subtractor & Full Adder/ Subtractor using NAND & NOR gates and to verify their truth tables. COMPONENTS REQUIRED IC Trainer kit, IC 7400, IC 7486 PRINCIPLE: : A half adder has no provision to add a carry from the lower order bits when binary numbers are added. When two input bits and a carry are to be added the number of input bits becomes three and the input combination increases to eight. For this full adder is used. Like half adder it also has a sum bit and a carry bit. The new carry generated is represented by ‘Cou’ and the carry generated from the previous addition is represented by “Cin” When two input bits and a borrow have to be subtracted the number of input bits equal to three and the input combinations increases to eight, for this a full subtractor is used. Truth table of Full Adder Truth table of Full Subtractor tput leas cin on Soa ame a i pi sot 0 0 0 o 0 o 0 oO 0 0 0 0 1 1 0 o 0 1 1 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 00 1 0 1 nr) 1 0 1 0 1 o 1 1 0 1 0 0 1 1 o o 41 1 1 0 0 0 Scanned with CamScannerCin: Cout Logic circuit of Full adder and Full adder using NAND gates anly eR <1 —T DD Sf 2p. Logie circuit of full subtractor and full subtractor using NAND gates PROCEDURE : 1. Verify whether all the wires and components are in good condition 2 Set up full adder circuit and feed all the input combinations 3, Observe the output corresponding to input combinations and enter it in the Truth table “£, Repeat the above steps for Full subtractor circuits RESULT: Full adder and the Full subtractor circuits are set up using logic gates and verified the result. Scanned with CamScannerExperiment No. 6 AIM: To verify the truth table of 4-to-1 multiplexer andl-to-4 demultiplexer. Realize the multiplexer using basic gates only. Also to construct and 8-to-1 multiplexer and 1-to-8 demultiplexer using blocks of 4-to-1 multiplexer and 1-to-4 demultiplexer Apparatus: 1. Digital Ic: a. IC 74151A - 4X1 multiplexer b. IC 74138 - 1X4 demultiplexer 2. +5 V DC Source x 2 3. Connecting wires THEORY: Part A - Multiplexers (Data Selectors) A multiplexer (MUX) or data selector is a logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output. The routing of the desired data input to the output is controlled by SELECT inputs (sometimes referred to as ADDRESS inputs). Fig.1 shows the functional diagram of a general multiplexer. In this diagram, the inputs and outputs are drawn as large arrows to indicate that they may constitute one or more signal lines. Normally there are 2n input lines and 1 select lines whose bit combinations determine which input is selected. Data inputs cunt Ons Select inputs. Fig.1 Functional diagram of digital multiplexer il Scanned with CamScannerThe multiplexer acts like a digitally controlled multi-position switch. The digital code applied to the SELECT inputs determines which data inputs will be switched to the output. For example, the output Z will equal the data input Dofor some particular input code; Z will equal D1 for another particular code, and so on. In other words, we can say that a multiplexer selects 1-out-of-N input data sources and transmits the selected data to a single output channel. This is called multiplexing. Basic 2-input Multiplexer Fig.2 shows the logic circuitry and function table for a 2-input multiplexer with data inputs Doand D1, and data select input S. The logic level applied to the S input determines which AND gate is enabled, so that its data input passes through the OR gate to the output Z. conan sme Do Data ———— inputs 2=D,5+D,S S$ Output (2) D, 0 Dy 1 D, Select input S (a) Logic diagram (b) Function table Fig.2 2-input multiplexer Scanned with CamScannerThe 4-input Multiplexer Fig.3 shows the logic circuitry for a 4-input multiplexer with data inputs Do, D1, D2, and Ds, and data select inputs Soand S1. The logic levels applied to the Soand S1 inputs determine which AND gate is enabled, so that its data input passes through the OR gate to the output Z. The function table in Fig.3 gives the output for the input select codes as Fig.3 4-input multiplexer Select inputs Output 8, S> z 0. «0 Dy o 4 D, 1 0 D, vot D, Select inputs S, S, (a) Logic diagram (b) Function table Fig.3 4-input multiplexer Le GSPo+ 5, Dy + SiS Dat S\So0Q Scanned with CamScannerThe 8-input Multiplexer The 2-4-8-16-input multiplexers are readily available in the TTL and CMOS families. These basic ICs can be combined for multiplexing a larger number of inputs. IC 74151 contains 8- input multiplexer with eight data inputs Do, D1, D2, D3, D4, Ds, De, and D7, and three data select inputs So, S1, and Sz. The pin diagram of IC 74151A is shown in DATA INPUTS DATA SELECT aan | Saar Vop D4 DS D6 D7 A B C D3. p2 D1 DO Y W STROBE GND oe ——— DATA INPUTS OUTPUTS Fig.4. Applications of Multiplexers Multiplexers find numerous and varied applications in digital systems of all types. These applications include data selection, data routing, operation sequencing, parallel-to-serial conversion, waveform generation, and logic function generation. Scanned with CamScannerA multiplexer takes sever one Demultiplexer (Data Distributors) performs the reve, Veral inputs and transmits one of them to the output. A demultiplexer Soletaenaiet Ts€ Operation; it takes a single input and distributes it over several outputs. different ae = Can be thought of as a ‘distributor’, since it transmits the same data to “nations. Thus, whereas a multiplexer is an N-to-1 device, a demultiplexer is a 1- to-N (or 2n) device. i ie a Fig.5 shows the functional diagram for a demultiplexer (DEMUX). The large arrows for inputs and Outputs can represent one or more lines. The ‘select’ input code determines the output line ‘o which the input data will be transmitted. In other words, the demultiplexer takes one input data source and selectively distributes it to 1-of-N output channels just like a multi-position switch. inputs Fig. Functional diagram of a general demultiplexer Scanned with CamScanner1-Line to 4-Line Demultiplexer 2.6 shows a L-line to 4-line demult es. The two select lines Soand Si on the input line will pass through th plexer circuit. The input data line goes to all of the AND enable only one gate at a time, and the data appearing 1e selected gate to the associated output line. Data eI input Oy = 05,5, Outputs: 0, 0, 0, 0, 0 0 0 D 0 0 Do 0 Doo Select inputs S, S, Do oo (a) Logic diagram (b) Truth table Fig.6 1-Line to 4-Line demultiplexer 4-Line to 8-Line Demultiplexer Fig.7 (a) shows the logic diagram for a demultiplexer that distributes one input line to eight output lines. The single data input line D is connected to all eight AND gates, but only one of these gates will be enabled by the select input lines. For example, with S2S1S0 = 000, only the AND gate Oowill be enabled, and the data input D will appear at output Oo. Other select codes cause input D to reach the other outputs. The truth table in Fig.7 (b) summarizes the operation. Scanned with CamScannerData input 2 = )}~o, DS,S,S, ~a0588 0; = [Link], = )}~0,=08,53, Select code Outputs Oy=0888, SS & 0,050, 0, 0, 0,0, 0, 000 00000000 x 001 00000000 0, = 0.5,8,5, 010 00000000 011 0000d000 0,=08,5,8, 100 000DdD0000 101 00000000 L- - 110 00000000 S }— 9 = 08,5,8, 111 Doooo0000 ES PRON ONO ONO 00; (a) Logie diagram (0) Truth table Fig.7 1-Line to 8-Line Demultiplexer PROCEDURE: 1. Place all circuit components on a breadboard. 2. Prepare circuitry using connecting wires. 3. Apply different level logic combinations to the inputs and observe the corresponding outputs. 4. Note down observed output level in corresponding observation [Link] demultiplexer Scanned with CamScannerExperiment No. 7 Design & Realize a combinational circuit that will accept a 2421 BCD code and drive a TIL -312 seven-segment display Apparatus: 1. Digital Ic: a. IC 7447 — BCD-to-seven segment decoder/drivers 2. +5 V DC Source x 2 3. Connecting wires THEORY: Part: A Encoder An encoder is a device whose inputs are decimal digits and/or alphabetic characters andwhose Outputs are the coded representation of those inputs, i.e. an encoder is a devicewhich converts familiar numbers or symbols into coded format. An encoder has a number of input lines, only one of which is activated at a giventime, and produces an N-bit output code depending on which input is activated. Fig.1 showsthe block diagram of an encoder with M inputs and N outputs. Here, the inputs are activeHIGH, which means they are normally LOW. Ao [—° Op Ay « [-0 0, Ap N [—0 O, Minputs Cc N-bit only one ° . out HIGH at D *, st atime E . R Anz |? One Rat [Ons Fig.1 Block diagram of encoder PART B Decoder Scanned with CamScannerA decoder is a logic circuit that converts an N-bit binary input code into M output lines such that only one output line is activated for each one of the possible combinations of inputs. In other words, we can say that a decoder identifies or recognizes or detects a particular code Fig.4 shows the general decoder diagram with N inputs and M outputs. Since each of the N inputs can be a 0 or a 1, there are 2v possible input combinations or codes. For each of these input combinations, only one of the M outputs will be active (HIGH), all the other outputs will remain inactive (LOW). Ao t— Do A, t—> D, A, > D. in ane : Decoder ne M P : : outputs. Ane [> Dat-2 Ans > Diy 2” input codes ‘Only one output is high for each input code Fig.4 General block diagram of a decoder Some decoders do not utilize all of the 2v possible input codes. For example, a BCD to decimal decoder has a 4-bit input code and 10 output lines that correspond to the 10 BCD code groups 0000 through 1001. Decoders of this type are often designed so that if any of the unused codes are applied to the input, none of the outputs will be activated. BCD-to-Seven Segment Decoder This type of decoder accepts the BCD code and provides outputs to energize seven segment display devices in order to produce a decimal read out. Sometimes, the hex A through F may be produced. Each segment is made up of a material that emits light when current is passed through it. The most commonly used materials include LEDs, incandescent filaments and LCDs. The LEDs generally provide greater illumination levels but require more power than that by LCDs. «Fig. shows a seven-segment display consisting of seven light emitting [Link] segments are designated by letters a-g as shown in the figure. By illuminating various combinations of segments as shown in Fig.5(b), the numbers 0-9 can be displayed. Fig.5(c) and Fig.5(d) show two types of LED display — the common-anode and the common-cathode types. Scanned with CamScanner(a) Letters used to designate the segments a a a a a f [ Je: ao Jol! o . o pe g ge ‘LE: oy a d d d d 0 1 2 3 4 a a a a a a Too [fh Bo [fo] o fo fh o fb fg fo e c e@ J-° cof k- E d d d d d (b) By causing different combinations of the segments to illuminate (shown with solid black), the numerals 0-9 can be displayed. +, abcde fg a bec def g = (c) A common-anode LED display (d) A common-cathode LED display Fig.5 The seven segment display ‘* In the common-anode type, a low voltage applied to an LED cathode allows current to flow through the diode, which causes it to emit light. In the common-cathode type, a high voltage applied to an LED anode causes the current to flow and the resulting light emission, + An 8-4-2-1 BCD-to-seven segment decoder is a logic circuit as shown in Fig. 6(a). The function table for such a decoder is shown in Fig.6(b). Since a 1 (HIGH) on any output line activates Scanned with CamScannerthat line, we assume that the display is of the common-cathode type. The K-map used to simplify the logic expression for driving segment b is shown inFig.6(c). Entries 10-15 are don't cares as usual. Since LEDs require considerable power, decoders often contain output drivers capable of supplying sufficient power. == m(0, 1, 2, 3,4, 7, 8,9) Don’t cares, d=Z m(10, 11, 12, 13, 14, 15) Ai Ao 00110, AN Ta ool | + |] + tI oii 1 al As oS a ef] |x x e421 } A | IL ay BCD input A, a tht sol TT Ay e Uy ; aR RAs AA, (6) K-map to derive simpltied expression (a) Logie circuit for diving segment (D) aor e424 BCD Seven segment code Decimaldgt =A, A, Ay @ bc do f @ 0 0000 177707 0 1 OO Ui oO do 0 oO 2 ooto0 11404 104 3 oot 1444008 4 0100 0411410014 5 o1o1 1071014 4 6 O) de te Cee the eet ake eal 7 ort 1 44 410000 8 1000 4444444 9 poor 1tttoiws (6) Function table Fig.6 BCD-to-seven segment decoder Scanned with CamScannerPROCEDURE: 1. Place all circuit components on a breadboard. 2. Prepare circuitry using connecting wires. ; 3. Apply different level logic combinations to the inputs and observe the corresponding outputs. 4. Note down observed output level in corresponding observation table. Scanned with CamScannerExperiment No. 8 Using basic logic gates, realize the R-S, J-K and D-flip flops with and without clock signal and verify their truth table. COMPONENTS REQUIRED Digital IC trainer kit, IC 7400, IC 7410, IC 7473, IC 7474, IC 7476 PRINCIPLE | | oo Flip flops are the basic building blocks in any memory systems since its output will remain in its State until it is forced to change it by some means SR FLIP FLOP Sand R stands for set and reset, There are four input combination possible at the inputs. Bu tS =R =1is forbidden since the output will be indeterminate. ca &-— X: Forbidden state TED SR FLIP FLOP Sand R stands for Set and Reset. There are four input combination Possible at the inputs. But S=R=1 is forbidden since the output will be indeterminate. = [Te [oa ; 2 Pat “aux Oo of k X: Forbidden state Scanned with CamScanner ilVK FLIP FLop The indeterminate output state of SR FF when fovea is avoided by converting it to a JK [Link] flip flop is switched on its output state is uncertain. When an initial state is to be assigned two separate inputs called preset and clear are used. They are active low inputs. cLkK— kK—{> LG MASTER SLAVE J K FLIP FLOP The race around condition of JK FF is rectified in master slave JK FF. Racing is toggling of output more than ones during the positive clock edge. MSIK FF is created by cascading two JK FF. The clock is fed to the first stage (Master) and is inverted and fed to the second stage (slave). This ensure that the master is always followed by the slave and eliminate the chance of racing. PRE‘ Waserach “SleveLach ——¥ ae Scanned with CamScannerDEF 't has only one input called a after a clock is applied, D FF and fed to K input, D s D input or Data input. The input data is transferred to the output an be derived from JK FF by using J input as D input and J is inverted Q Input D4 cLkK— > TFF T stands for Toggle. The output toggles when a clock pulse is applied. T FF can be derived from JK FF by shorting J and K input. clock clock =) J. _ PROCEDURE: 1, Test all components and IC packages using digital IC tester and multimeter 2. Set up FF using Gates and verify their truth tables 3. Verify the Truth tables of 7473, 7474, and 7476 ICs RESULT: R The flip flopStip flop, Gated RS flip flop, D flip flop, T flip flop, JK flip flop and MS JK flip flops were set up using NAND gates and verified. ICs 7474, 7473 and 7476 are familiarized, Scanned with CamScannerExperiment No Construction and verification of operation of 4-bit ring counter using D flip flop. Apparatus: Logic trainer kit, D flip flops(IC 74173), wires. Theory: Ring counter is constructed by modifying the Serial In Serial Out shift register. The basic ring counter can be obtained by connecting the last output to first input. When clock si is applied. data is shifted in a circular manner or ina closed ring, so it is called a ring counter. —po Qo Di Qi D2 Q2 D3 Q3 wo a Q Bl CLK | | I Proceduré 1, Connect d flip flops as per circuit diagram. 2. Connect clock signal to logic source 3. Apply clock signal continuously and observe the output 4. If all outputs are zero then disconnect input to first flip flop 5. Apply 1 to it and give clock signal. 6. Reconnect QO to D3 and check operation of this circuit 7. Observe the out put. 8. Switch off power supply Scanned with CamScannerExperiment No:10 Perform input/output operations on parallel in/Parallel out and Serial /Serial out registers using clock. Also exercise loading only one of multiple values into the register using multiplexer. Apparatus: Logic trainer kit, D flip flop (IC 74143), wires 01 ry: Shift register is used to move the data, To move data, it must be stored. So shift register actually stores data and moves it to left, right as per signal given to it. Its various types are: ~Serial In Serial Out ~Serial In Parallel Out -Parallel In Serial Out -Parallel In Parallel Out As flip flops are capable to store data (1 bit in a flip flop), they are used to construct shift registers Serial In: Output of one flip flop is input of another. Data is serially given ic. only first flip flop receives data; it is shifted to next flip flops. Serial Out: Data is taken out from last flip flop Parallel In: All flip flops are loaded simultaneously Parallel Out: data is taken parallely by taking outputs from all flip flops at same time. Scanned with CamScannerSerial In. ——— / Do 20 DL Ql D2 Ds Q3 Serial Ou % q & w CLK eRe Parallel Out Parallel In DO. QO DQ D2 @ D3 Q| a a a CLK 4 | Parallel Out Scanned with CamScannerParallel In \ an Lol Shit Dd pai Ure Ql Procedure: 1. Connect flip flops as per given diagram 2. Connect inputs to Q3, and QO to logic indicator. 3. Apply clock and data train to Q3, observe output at Q0(SISO) 4. For SIPO, observe outputs at all Q’s by connecting all to logic indicators 5, Repeat for parallel in by connecting D’s to logic sources and outputs at QO for PISO, Q's for PISO 6. Switch off supply. Scanned with CamScanner