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The document defines constants for different exception types and stack pointers in ARM architectures. It includes macros for saving and restoring processor context during exceptions and defines the vector table entries that contain the address of exception handlers for each exception type for different execution environments and stack pointers.

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.section .text.

vectors

.equ AARCH64_SYNC_SP0, 0x1

.equ AARCH64_IRQ_SP0, 0x2
.equ AARCH64_FIQ_SP0, 0x3
.equ AARCH64_SERR_SP0, 0x4

.equ AARCH64_SYNC_SPX, 0x11

.equ AARCH64_IRQ_SPX, 0x12
.equ AARCH64_FIQ_SPX, 0x13
.equ AARCH64_SERR_SPX, 0x14

.equ LOWER_SYNC_AARCH64, 0x21

.equ LOWER_FIQ_AARCH64, 0x22
.equ LOWER_IRQ_AARCH64, 0x23
.equ LOWER_SERR_AARCH64, 0x24

.equ LOWER_SYNC_AARCH32, 0x31

.equ LOWER_FIQ_AARCH32, 0x32
.equ LOWER_IRQ_AARCH32, 0x33
.equ LOWER_SERR_AARCH32, 0x34

.macro save_context \exception_type

/* Store GP registers */
stp x0, x1, [sp, #-16]!
stp x2, x3, [sp, #-16]!
stp x4, x5, [sp, #-16]!
stp x6, x7, [sp, #-16]!
stp x8, x9, [sp, #-16]!
stp x10, x11, [sp, #-16]!
stp x12, x13, [sp, #-16]!
stp x14, x15, [sp, #-16]!
stp x16, x17, [sp, #-16]!
stp x18, x19, [sp, #-16]!
stp x20, x21, [sp, #-16]!
stp x22, x23, [sp, #-16]!
stp x24, x25, [sp, #-16]!
stp x26, x27, [sp, #-16]!
stp x28, x29, [sp, #-16]!
stp x30, xzr, [sp, #-16]!

/* Store SPSR */
mrs x20, spsr_el1
stp x20, xzr, [sp, #-16]!

/* Store ELR */
mrs x20, elr_el1
stp x20, xzr, [sp, #-16]!

mov x20, #(\exception_type)

mrs x21, esr_el1
stp x20, x21, [sp, #-16]!
.endm

.macro restore_context
/* Drop exception ESR and exception type */
add sp, sp, #16

ldp x20, xzr, [sp], #16

msr elr_el1, x20

ldp x20, xzr, [sp], #16

msr spsr_el1, x20

ldp x30, xzr, [sp], #16

ldp x28, x29, [sp], #16
ldp x26, x27, [sp], #16
ldp x24, x25, [sp], #16
ldp x22, x23, [sp], #16
ldp x20, x21, [sp], #16
ldp x18, x19, [sp], #16
ldp x16, x17, [sp], #16
ldp x14, x15, [sp], #16
ldp x12, x13, [sp], #16
ldp x10, x11, [sp], #16
ldp x8, x9, [sp], #16
ldp x6, x7, [sp], #16
ldp x4, x5, [sp], #16
ldp x2, x3, [sp], #16
ldp x0, x1, [sp], #16
.endm

.macro save_trapped_sp
msr x20, sp_el0
str x20, [sp, #16]
.endm

.macro save_nested_sp
mov x20, sp
add x20, x20, #288
str x20, [sp, #16]
.endm

.macro restore_trapped_sp
ldr x20, [sp, #16]
msr sp_el0, x20
.endm

.section .text.vectors

.balign 2048
.global _vector_table
_vector_table:
/* Current EL with SP0 */
b _curr_el_sp0_sync
.balign 128
b _curr_el_sp0_fiq
.balign 128
b _curr_el_sp0_irq
.balign 128
b _curr_el_sp0_serror
.balign 128
/* Current EL with SPX */
b _curr_el_spx_sync
.balign 128
b _curr_el_spx_fiq
.balign 128
b _curr_el_spx_irq
.balign 128
b _curr_el_spx_serror
.balign 128

/* Lower EL in arrch64 mode */

b _lower_el_aarch64_sync
.balign 128
b _lower_el_aarch64_fiq
.balign 128
b _lower_el_aarch64_irq
.balign 128
b _lower_el_aarch64_serror

/* Lower EL in aarch32 mode */

b _lower_el_aarch32_sync
.balign 128
b _lower_el_aarch32_fiq
.balign 128
b _lower_el_aarch32_irq
.balign 128
b _lower_el_aarch32_serror

.global _curr_el_sp0_sync
_curr_el_sp0_sync:
save_context AARCH64_SYNC_SP0